Datasheet

Section 16 Watchdog Timer
Rev. 2.00 Jul. 04, 2007 Page 335 of 692
REJ09B0309-0200
Section 16 Watchdog Timer
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an
internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus
allowing it to overflow.
When this watchdog timer function is not needed, the WDT can be used as an interval timer. In
interval timer operation, an interval timer interrupt is generated each time the counter overflows.
16.1 Features
The WDT features are described below.
• Selectable from eleven counter input clocks
Ten internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φ
W
/16,
and φ
W
/256) or the on-chip watchdog timer oscillator can be selected as the timer-counter
clock.
• Watchdog timer mode
If the counter overflows, this LSI is internally reset.
• Interval timer mode
If the counter overflows, an interval timer interrupt is generated.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The WDT is operating as the initial value. For details, refer to section 6.4,
Module Standby Function.)