Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16-Bit 4 MHz I/O number 75

Table Of Contents

Cover
Notes regarding these materials
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Figures
Tables
Section 1 Overview
- 1.1 Features
- 1.2 Internal Block Diagram
- 1.3 Pin Assignment
- 1.4 Pin Functions
Section 2 CPU
- 2.1 Address Space and Memory Map
- 2.2 Register Configuration
- 2.3 Data Formats
  - 2.3.1 General Register Data Formats
  - 2.3.2 Memory Data Formats
- 2.4 Instruction Set
  - 2.4.1 Table of Instructions Classified by Function
  - 2.4.2 Basic Instruction Formats
- 2.5 Addressing Modes and Effective Address Calculation
  - 2.5.1 Addressing Modes
  - 2.5.2 Effective Address Calculation
- 2.6 Basic Bus Cycle
  - 2.6.1 Access to On-Chip Memory (RAM, ROM)
  - 2.6.2 On-Chip Peripheral Modules
- 2.7 CPU States
- 2.8 Usage Notes
Section 3 Exception Handling
- 3.1 Exception Sources and Vector Address
- 3.2 Reset
  - 3.2.1 Reset Exception Handling
  - 3.2.2 Interrupt Immediately after Reset
- 3.3 Interrupts
- 3.4 Stack Status after Exception Handling
- 3.5 Usage Notes
Section 4 Interrupt Controller
- 4.1 Features
- 4.2 Input/Output Pins
- 4.3 Register Descriptions
- 4.4 Interrupt Sources
  - 4.4.1 External Interrupts
  - 4.4.2 Internal Interrupts
- 4.5 Interrupt Exception Handling Vector Table
- 4.6 Operation
  - 4.6.1 Interrupt Exception Handling Sequence
  - 4.6.2 Interrupt Response Times
- 4.7 Usage Notes
Section 5 Clock Pulse Generator
- 5.1 Register Description
  - 5.1.1 SUB32k Control Register (SUB32CR)
  - 5.1.2 Oscillator Control Register (OSCCR)
- 5.2 System Clock Generator
- 5.3 Subclock Generator
- 5.4 Prescalers
  - 5.4.1 Prescaler S
  - 5.4.2 Prescaler W
- 5.5 Usage Notes
Section 6 Power-Down Modes
- 6.1 Register Descriptions
- 6.2 Mode Transitions and States of LSI
- 6.3 Direct Transition
- 6.4 Module Standby Function
- 6.5 Usage Notes
  - 6.5.1 Standby Mode Transition and Pin States
  - 6.5.2 Notes on External Input Signal Changes before/after Standby Mode
Section 7 ROM
- 7.1 Block Configuration
- 7.2 Register Descriptions
- 7.3 On-Board Programming Modes
  - 7.3.1 Boot Mode
  - 7.3.2 Programming/Erasing in User Program Mode
- 7.4 Using RAM to Emulate Flash Memory
- 7.5 Flash Memory Programming/Erasing
- 7.6 Program/Erase Protection
- 7.7 Programmer Mode
- 7.8 Power-Down States for Flash Memory
- 7.9 Notes on Setting Module Standby Mode
Section 8 RAM
Section 9 I/O Ports
- 9.1 Port 1
- 9.2 Port 3
- 9.3 Port 4
- 9.4 Port 5
- 9.5 Port 6
- 9.6 Port 7
- 9.7 Port 8
- 9.8 Port 9
- 9.9 Port A
- 9.10 Port B
- 9.11 Port C
- 9.12 Port E
- 9.13 Port F
- 9.14 Input/Output Data Inversion
  - 9.14.1 Serial Port Control Register, Serial Port Control Register 2 (SPCR, SPCR2)
- 9.15 Port Function Switch
  - 9.15.1 Port Function Control Register (PFCR)
- 9.16 Usage Notes
  - 9.16.1 How to Handle Unused Pin
  - 9.16.2 Input Characteristics Difference due to Pin Function
Section 10 Realtime Clock (RTC)
- 10.1 Features
- 10.2 Input/Output Pin
- 10.3 Register Descriptions
- 10.4 Operation
- 10.5 Interrupt Sources
- 10.6 Usage Notes
  - 10.6.1 Note on Clock Count
  - 10.6.2 Note when Using RTC Interrupts
Section 11 Timer C
- 11.1 Features
- 11.2 Input/Output Pins
- 11.3 Register Descriptions
- 11.4 Timer Operation
- 11.5 Timer C Operation States
Section 12 Timer F
- 12.1 Features
- 12.2 Input/Output Pins
- 12.3 Register Descriptions
- 12.4 Operation
- 12.5 Timer F Operating States
- 12.6 Usage Notes
Section 13 Timer G
- 13.1 Features
- 13.2 Input/Output Pins
- 13.3 Register Descriptions
- 13.4 Noise Canceller
- 13.5 Operation
- 13.6 Timer G Operation Modes
- 13.7 Usage Notes
  - 13.7.1 Internal Clock Switching and TCG Operation
  - 13.7.2 Notes on Port Mode Register Modification
- 13.8 Timer G Application Example
Section 14 16-Bit Timer Pulse Unit (TPU)
- 14.1 Features
- 14.2 Input/Output Pins
- 14.3 Register Descriptions
- 14.4 Interface to CPU
  - 14.4.1 16-Bit Registers
  - 14.4.2 8-Bit Registers
- 14.5 Operation
- 14.6 Interrupt Sources
- 14.7 Operation Timing
  - 14.7.1 Input/Output Timing
  - 14.7.2 Interrupt Signal Timing
- 14.8 Usage Notes
Section 15 Asynchronous Event Counter (AEC)
- 15.1 Features
- 15.2 Input/Output Pins
- 15.3 Register Descriptions
- 15.4 Operation
- 15.5 Operating States of Asynchronous Event Counter
- 15.6 Usage Notes
Section 16 Watchdog Timer
- 16.1 Features
- 16.2 Register Descriptions
- 16.3 Operation
- 16.4 Interrupt
- 16.5 Usage Notes
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
- 17.1 Features
- 17.2 Input/Output Pins
- 17.3 Register Descriptions
- 17.4 Operation in Asynchronous Mode
- 17.5 Operation in Clock Synchronous Mode
- 17.6 Multiprocessor Communication Function
  - 17.6.1 Multiprocessor Serial Data Transmission
  - 17.6.2 Multiprocessor Serial Data Reception
- 17.7 IrDA Operation
- 17.8 Interrupt Requests
- 17.9 Usage Notes
Section 18 Serial Communication Interface 4 (SCI4)
- 18.1 Features
- 18.2 Input/Output Pins
- 18.3 Register Descriptions
- 18.4 Operation
- 18.5 Interrupt Sources
- 18.6 Usage Notes
Section 19 14-Bit PWM
- 19.1 Features
- 19.2 Input/Output Pins
- 19.3 Register Descriptions
  - 19.3.1 PWM Control Register (PWCR)
  - 19.3.2 PWM Data Register (PWDR)
- 19.4 Operation
- 19.5 Usage Notes
  - 19.5.1 Timing of Writing to PWDR and Reflection in the PWM Waveform
Section 20 A/D Converter
- 20.1 Features
- 20.2 Input/Output Pins
- 20.3 Register Descriptions
- 20.4 Operation
- 20.5 Example of Use
- 20.6 A/D Conversion Accuracy Definitions
- 20.7 Usage Notes
Section 21 LCD Controller/Driver
- 21.1 Features
- 21.2 Input/Output Pins
- 21.3 Register Descriptions
- 21.4 Operation
- 21.5 Usage Notes
  - 21.5.1 Pin Handling when LCD Controller/Driver is not Used
  - 21.5.2 Pin Handling when 3-V Constant-Voltage Power Supply Circuit is not Used
Section 22 I2C Bus Interface 2 (IIC2)
- 22.1 Features
- 22.2 Input/Output Pins
- 22.3 Register Descriptions
- 22.4 Operation
- 22.5 Interrupt Request
- 22.6 Bit Synchronous Circuit
- 22.7 Usage Notes
Section 23 Power-On Reset Circuit
- 23.1 Feature
- 23.2 Operation
  - 23.2.1 Power-On Reset Circuit
Section 24 Address Break
- 24.1 Register Descriptions
- 24.2 Operation
- 24.3 Operating States of Address Break
Section 25 List of Registers
- 25.1 Register Addresses (Address Order)
- 25.2 Register Bits
- 25.3 Register States in Each Operating Mode
Section 26 Electrical Characteristics
- 26.1 Absolute Maximum Ratings for F-ZTAT Version
- 26.2 Electrical Characteristics for F-ZTAT Version
- 26.3 Absolute Maximum Ratings for Masked ROM Version
- 26.4 Electrical Characteristics for Masked ROM Version
- 26.5 Operation Timing
- 26.6 Output Load Circuit
- 26.7 Recommended Resonators
- 26.8 Usage Note
Appendix
- A. Instruction Set
- B. I/O Ports
  - B.1 I/O Port Block Diagrams
  - B.2 Port States in Each Operating State
- C. Product Part No. Lineup
- D. Package Dimensions
Main Revisions and Additions in this Edition
Index
Colophon
Address List
Back Cover

Rev. 2.00 Jul. 04, 2007 Page xxxvi of xl

Section 7 ROM

Table 7.1 Setting Programming Modes ................................................................................ 134

Table 7.2 Boot Mode Operation ........................................................................................... 136

Table 7.3 System Clock Frequencies for which Automatic Adjustment of

LSI Bit Rate is Possible ........................................................................................ 137

Table 7.4 Reprogram Data Computation Table .................................................................... 142

Table 7.5 Additional-Program Data Computation Table ...................................................... 142

Table 7.6 Programming Time............................................................................................... 142

Table 7.7 Flash Memory Operating States............................................................................ 147

Section 10 Realtime Clock (RTC)

Table 10.1 Pin Configuration.................................................................................................. 212

Table 10.2 Interrupt Sources................................................................................................... 224

Section 11 Timer C

Table 11.1 Pin Configuration.................................................................................................. 228

Table 11.2 Timer C Operation States ..................................................................................... 234

Section 12 Timer F

Table 12.1 Pin Configuration.................................................................................................. 236

Table 12.2 Timer F Operating States...................................................................................... 247

Section 13 Timer G

Table 13.1 Pin Configuration.................................................................................................. 255

Table 13.2 Timer G Operation Modes.................................................................................... 265

Table 13.3 Internal Clock Switching and TCG Operation...................................................... 266

Table 13.4 Input Capture Input Signal Input Edges Due to Input Capture

Input Pin Switching, and Conditions for Their Occurrence.................................. 268

Table 13.5 Input Capture Input Signal Input Edges Due to Noise Canceller Function

Switching, and Conditions for Their Occurrence ................................................. 268

Section 14 16-Bit Timer Pulse Unit (TPU)

Table 14.1 TPU Functions ...................................................................................................... 272

Table 14.2 Pin Configuration.................................................................................................. 273

Table 14.3 CCLR1 and CCLR0 (Channels 1 and 2)............................................................... 276

Table 14.4 TPSC2 to TPSC0 (Channel 1) .............................................................................. 276

Table 14.5 TPSC2 to TPSC0 (Channel 2) .............................................................................. 277

Table 14.6 MD1 to MD0 ........................................................................................................ 278

Table 14.7 TIOR_1 (Channel 1) ............................................................................................. 279

Table 14.8 TIOR_2 (Channel 2) ............................................................................................. 280

Table 14.9 TIOR_1 (Channel 1) ............................................................................................. 281

Table 14.10 TIOR_2 (Channel 2) ......................................................................................... 282

Table 14.11 Counter Combination in Operation with Cascaded Connection ....................... 298