Datasheet

Section 16 Watchdog Timer
Rev. 2.00 Jul. 04, 2007 Page 341 of 692
REJ09B0309-0200
16.2.4 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit Bit Name
Initial
Value
R/W Description
7 to 4  All 1  Reserved
These bits are always read as 1.
3
2
1
0
CKS3
CKS2
CKS1
CKS0
0
0
0
0
R/W
R/W
R/W
R/W
Clock Select 3 to 0
Select the clock to be input to TCWD.
00xx: On-chip WDT oscillator
0100: Internal clock: counts on φ
W
/16
0101: Internal clock: counts on φ
W
/256
011x: Reserved
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ/8192
For the overflow periods of the on-chip WDT oscillator,
see section 26, Electrical Characteristics.
In active (medium-speed), sleep (medium-speed),
subactive, and subsleep modes, the 00xx value and the
interval timer mode cannot be set simultaneously.
In subactive and subsleep modes, when the subclock
frequency is φ
W
/8, the 010x value and the interval timer
mode cannot be set simultaneously.
[Legend]
x: Don't care