Datasheet

Section 16 Watchdog Timer
Rev. 2.00 Jul. 04, 2007 Page 342 of 692
REJ09B0309-0200
16.3 Operation
16.3.1 Watchdog Timer Mode
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear
the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is
written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in
TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write
accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has
reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal
reset signal is output for a period of 512 clock cycles of the on-chip watchdog timer oscillator.
TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that
value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set,
according to the TCWD set value.
Figure 16.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when φ = 4 MHz
4 × 10
6
× 30 × 10
–3
= 14.6
8192
TCWD overflow
H'FF
H'00
Internal reset
signal
H'F1
TCWD
count value
H'F1 written
to TCWD
H'F1 written to TCWD Reset generated
Start
512 clock cycles
(on-chip WDT oscillator)
Therefore, 256 – 15 = 241 (H'F1) is set in TCWD.
Figure 16.2 Example of Watchdog Timer Operation