Datasheet

Section 16 Watchdog Timer
Rev. 2.00 Jul. 04, 2007 Page 344 of 692
REJ09B0309-0200
16.4 Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF
flag must be cleared to 0 in the interrupt handling routine.
16.5 Usage Notes
16.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode
If modes are switched between watchdog timer and interval timer, while the WDT is operating, an
error may occur in the count value. Software must stop the watchdog timer (by clearing the
WDON bit to 0) before switching modes.
16.5.2 Module Standby Mode Control
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register
WD1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is
set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter
module standby mode but continues operating. When the WDON bit is cleared to 0 by software
after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the
watchdog timer enters module standby mode.
16.5.3 Writing to Timer Counter WD (TCWD) with the On-Chip Watchdog Timer
Oscillator Selected
When the timer counter WD (TCWD) is written to with the on-chip watchdog timer oscillator
selected as the clock to drive the counter, updating of values read from TCWD requires up to (on-
chip watchdog timer oscillator overflow time)/256. The watchdog timer does not overflow
between writing of the new value to the register and updating of the read values.