Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 355 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ
W
/2 clock (n = 0)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When φ
W
/2 clock is selected in subactive mode and
subsleep mode, the SCI3 is only enabled when φ
W
/2
clock is selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 17.3.8, Bit Rate
Register (BRR). n is the decimal representation of the
value of n in BRR (see section 17.3.8, Bit Rate
Register (BRR)).