Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 357 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 17.6, Multiprocessor Communication Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, the TEI3 interrupt request is
enabled. TEI3 can be released by clearing bit TDRE to
0 and clearing bit TEND to 0 in SSR, or by clearing bit
TEIE to 0.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 0 and 1
Select the clock source.
Asynchronous mode:
00: Internal baud rate generator (The SCK3 pin
functions as an I/O port)
01: Internal baud rate generator (Outputs a clock of the
same frequency as the bit rate from the SCK3 pin)
10: External clock (Inputs a clock with a frequency 16
times the bit rate from the SCK3 pin)
11: Reserved
Clock synchronous mode:
00: Internal clock (The SCK3 pin functions as clock
output)
01: Reserved
10: External clock (The SCK3 pin functions as clock
input)
11: Reserved