Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 359 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
5 OER 0 R/(W)* Overrun Error
[Setting condition]
• An overrun error occurs in reception
[Clearing condition]
• Writing of 0 to bit OER after reading OER = 1
When bit RE in SCR is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost.
Reception cannot be continued with bit OER set to 1,
and in clock synchronous mode, transmission cannot
be continued either.
4 FER 0 R/(W)* Framing Error
[Setting condition]
• A framing error occurs in reception
[Clearing condition]
• Writing of 0 to bit FER after reading FER = 1
When bit RE in SCR is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked.
When a framing error occurs, the receive data is
transferred to RDR but bit RDRF is not set. Reception
cannot be continued with bit FER set to 1.
In clock synchronous mode, neither transmission nor
reception is possible when bit FER is set to 1.