Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 361 of 692
REJ09B0309-0200
17.3.8 Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that specifies the bit rate. BRR is initialized to H'FF.
Tables 17.3 and 17.4 show examples of the N setting in BRR and the n setting in bits CKS1 and
CKS0 in SMR in asynchronous mode. Table 17.6 shows the maximum bit rate for each frequency
in asynchronous mode. The values shown in these tables are values in active (high-speed) mode.
When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit rate is twice the
values shown in table 17.6.
Tables 17.7 (1) and (2) show examples of the N setting in BRR and the n setting in bits CKS1 and
CKS0 in SMR in clock synchronous mode. The values shown in these tables are values in active
(high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates
can be obtained by the following formulas:
[Asynchronous Mode, ABCS = 0]
N =
φ
32 × 2
2n
× B
– 1
Error (%) = × 100
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 17.3)
R (bit rate in left-hand column in table 17.3)
[Asynchronous Mode, ABCS = 1*]
N =
φ
16 × 2
2n
× B
– 1
Error (%) = × 100
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 17.4)
R (bit rate in left-hand column in table 17.4)
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The correspondence between n and the clock is shown in table 17.5)
Note: * Only supported by the SCI3_1 interface.