Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 378 of 692
REJ09B0309-0200
17.4 Operation in Asynchronous Mode
Figure 17.2 shows the general format for asynchronous serial communication. Each frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In reception in asynchronous mode, synchronization is with falling
edges of the start bits. The data is sampled on the 8th pulse of a clock signal with a frequency 16
times the bit rate, so that the transferred data is latched at the center of each bit. When the ABCS
bit in SEMR is set to 1, data is sampled on the 4th pulse of a clock with a frequency 8 times the bit
rate*. Internally, the SCI3 has independent transmitter and receiver units, which enables full
duplex operation. Both the transmitter and the receiver also have a double-buffered structure, so
data can be read or written during transmission or reception, enabling continuous data transfer.
Table 17.9 shows the 16 data transfer formats that can be set in asynchronous mode. The format is
selected by the settings in SMR as shown in table 17.10.
Note: Only supported by the SCI3_1 interface.
LSB
Start
bit
MSB
Mark state
Stop bit
Transmit/receive data
1
Serial
data
Parity
bit
1 bit 1 or
2 bits
5, 7, or 8 bits
1 bit,
or none
One unit of transfer data (character or frame)
Figure 17.2 Data Format in Asynchronous Communication