Datasheet

Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 379 of 692
REJ09B0309-0200
17.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3's serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock signal is input on
the SCK3 pin, its frequency should be 16 times the bit rate (or 8 times the bit rate when the ABCS
bit in SEMR is set to 1*). For details on selection of the clock source, see table 17.11. When the
SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency
of the clock output in this case is equal to the bit rate, and the phase is such that rising edges of the
clock signal are in the middle of each bit of the data to be transferred, as shown in figure 17.3.
Note: * Only supported by the SCI3_1 interface.
0
1 character (frame)
D0 D1 D2 D3 D4 D5 D6 D7 0/1
11
Clock
Serial data
Figure 17.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)