Datasheet
Table Of Contents
- Cover
- Notes regarding these materials
- General Precautions on Handling of Product
- Configuration of This Manual
- Preface
- Contents
- Figures
- Tables
- Section 1 Overview
- Section 2 CPU
- Section 3 Exception Handling
- Section 4 Interrupt Controller
- 4.1 Features
- 4.2 Input/Output Pins
- 4.3 Register Descriptions
- 4.3.1 Interrupt Edge Select Register (IEGR)
- 4.3.2 Wakeup Edge Select Register (WEGR)
- 4.3.3 Interrupt Enable Register 1 (IENR1)
- 4.3.4 Interrupt Enable Register 2 (IENR2)
- 4.3.5 Interrupt Request Register 1 (IRR1)
- 4.3.6 Interrupt Request Register 2 (IRR2)
- 4.3.7 Wakeup Interrupt Request Register (IWPR)
- 4.3.8 Interrupt Priority Registers A to F (IPRA to IPRF)
- 4.3.9 Interrupt Mask Register (INTM)
- 4.4 Interrupt Sources
- 4.5 Interrupt Exception Handling Vector Table
- 4.6 Operation
- 4.7 Usage Notes
- Section 5 Clock Pulse Generator
- 5.1 Register Description
- 5.2 System Clock Generator
- 5.3 Subclock Generator
- 5.4 Prescalers
- 5.5 Usage Notes
- 5.5.1 Note on Resonators and Resonator Circuits
- 5.5.2 Notes on Board Design
- 5.5.3 Definition of Oscillation Stabilization Wait Time
- 5.5.4 Note on Subclock Stop State
- 5.5.5 Note on the Oscillation Stabilization of Resonators
- 5.5.6 Note on Using On-Chip Power-On Reset
- 5.5.7 Note on Using the On-Chip Emulator
- Section 6 Power-Down Modes
- 6.1 Register Descriptions
- 6.2 Mode Transitions and States of LSI
- 6.3 Direct Transition
- 6.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
- 6.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode
- 6.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
- 6.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode
- 6.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode
- 6.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
- 6.3.7 Notes on External Input Signal Changes before/after Direct Transition
- 6.4 Module Standby Function
- 6.5 Usage Notes
- Section 7 ROM
- Section 8 RAM
- Section 9 I/O Ports
- Section 10 Realtime Clock (RTC)
- 10.1 Features
- 10.2 Input/Output Pin
- 10.3 Register Descriptions
- 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR)
- 10.3.2 Minute Data Register (RMINDR)
- 10.3.3 Hour Data Register (RHRDR)
- 10.3.4 Day-of-Week Data Register (RWKDR)
- 10.3.5 RTC Control Register 1 (RTCCR1)
- 10.3.6 RTC Control Register 2 (RTCCR2)
- 10.3.7 Clock Source Select Register (RTCCSR)
- 10.3.8 RTC Interrupt Flag Register (RTCFLG)
- 10.4 Operation
- 10.5 Interrupt Sources
- 10.6 Usage Notes
- Section 11 Timer C
- Section 12 Timer F
- Section 13 Timer G
- Section 14 16-Bit Timer Pulse Unit (TPU)
- 14.1 Features
- 14.2 Input/Output Pins
- 14.3 Register Descriptions
- 14.3.1 Timer Control Register (TCR)
- 14.3.2 Timer Mode Register (TMDR)
- 14.3.3 Timer I/O Control Register (TIOR)
- 14.3.4 Timer Interrupt Enable Register (TIER)
- 14.3.5 Timer Status Register (TSR)
- 14.3.6 Timer Counter (TCNT)
- 14.3.7 Timer General Register (TGR)
- 14.3.8 Timer Start Register (TSTR)
- 14.3.9 Timer Synchro Register (TSYR)
- 14.4 Interface to CPU
- 14.5 Operation
- 14.6 Interrupt Sources
- 14.7 Operation Timing
- 14.8 Usage Notes
- 14.8.1 Module Standby Function Setting
- 14.8.2 Input Clock Restrictions
- 14.8.3 Caution on Period Setting
- 14.8.4 Contention between TCNT Write and Clear Operation
- 14.8.5 Contention between TCNT Write and Increment Operation
- 14.8.6 Contention between TGR Write and Compare Match
- 14.8.7 Contention between TGR Read and Input Capture
- 14.8.8 Contention between TGR Write and Input Capture
- 14.8.9 Contention between Overflow and Counter Clearing
- 14.8.10 Contention between TCNT Write and Overflow
- 14.8.11 Multiplexing of I/O Pins
- 14.8.12 Interrupts when Module Standby Function is Used
- 14.8.13 Output Conditions for 0% Duty and 100% Duty
- Section 15 Asynchronous Event Counter (AEC)
- Section 16 Watchdog Timer
- Section 17 Serial Communications Interface 3 (SCI3, IrDA)
- 17.1 Features
- 17.2 Input/Output Pins
- 17.3 Register Descriptions
- 17.3.1 Receive Shift Register (RSR)
- 17.3.2 Receive Data Register (RDR)
- 17.3.3 Transmit Shift Register (TSR)
- 17.3.4 Transmit Data Register (TDR)
- 17.3.5 Serial Mode Register (SMR)
- 17.3.6 Serial Control Register (SCR)
- 17.3.7 Serial Status Register (SSR)
- 17.3.8 Bit Rate Register (BRR)
- 17.3.9 Serial Port Control Register (SPCR)
- 17.3.10 Serial Port Control Register 2 (SPCR2)
- 17.3.11 IrDA Control Register (IrCR)
- 17.3.12 Serial Extended Mode Register (SEMR)
- 17.4 Operation in Asynchronous Mode
- 17.5 Operation in Clock Synchronous Mode
- 17.6 Multiprocessor Communication Function
- 17.7 IrDA Operation
- 17.8 Interrupt Requests
- 17.9 Usage Notes
- 17.9.1 Break Detection and Processing
- 17.9.2 Mark State and Break Sending
- 17.9.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
- 17.9.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
- 17.9.5 Note on Switching SCK3 Pin Function
- 17.9.6 Relation between Writing to TDR and Bit TDRE
- 17.9.7 Relation between RDR Reading and bit RDRF
- 17.9.8 Transmit and Receive Operations when Making State Transition
- 17.9.9 Setting in Subactive or Subsleep Mode
- 17.9.10 Oscillator when Serial Communications Interface 3 is Used
- Section 18 Serial Communication Interface 4 (SCI4)
- Section 19 14-Bit PWM
- Section 20 A/D Converter
- Section 21 LCD Controller/Driver
- Section 22 I2C Bus Interface 2 (IIC2)
- 22.1 Features
- 22.2 Input/Output Pins
- 22.3 Register Descriptions
- 22.3.1 I2C Bus Control Register 1 (ICCR1)
- 22.3.2 I2C Bus Control Register 2 (ICCR2)
- 22.3.3 I2C Bus Mode Register (ICMR)
- 22.3.4 I2C Bus Interrupt Enable Register (ICIER)
- 22.3.5 I2C Bus Status Register (ICSR)
- 22.3.6 Slave Address Register (SAR)
- 22.3.7 I2C Bus Transmit Data Register (ICDRT)
- 22.3.8 I2C Bus Receive Data Register (ICDRR)
- 22.3.9 I2C Bus Shift Register (ICDRS)
- 22.4 Operation
- 22.5 Interrupt Request
- 22.6 Bit Synchronous Circuit
- 22.7 Usage Notes
- 22.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition
- 22.7.2 Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)
- 22.7.3 Restriction on Transfer Rate Setting in Multimaster Operation
- 22.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation
- 22.7.5 Usage Note on Master Receive Mode
- Section 23 Power-On Reset Circuit
- Section 24 Address Break
- Section 25 List of Registers
- Section 26 Electrical Characteristics
- Appendix
- Main Revisions and Additions in this Edition
- Index
- Colophon
- Address List
- Back Cover
Section 17 Serial Communications Interface 3 (SCI3, IrDA)
Rev. 2.00 Jul. 04, 2007 Page 396 of 692
REJ09B0309-0200
17.6 Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 17.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is
set to 1 at this time, an RXI3 interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.