Datasheet

Section 18 Serial Communication Interface 4 (SCI4)
Rev. 2.00 Jul. 04, 2007 Page 417 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
2 SRES 0 R/W Forcible Reset
When the internal sequencer is forcibly initialized, 1
should be written to this bit. When 1 is written to this
flag, the internal sequencer is forcibly reset and then
this flag is automatically cleared to 0. Note that the
values of the internal registers are retained. (The
TDRE flag in SCSR4 is set to 1 and the RDRF, ORER,
and TEND flags are cleared to 0. The TE and RE bits
in SCR4 are cleared to 0.)
0: Normal operation
1: Internal sequencer is forcibly reset
1 TE 0 R/W Transmit Enable
Enables or disables start of the SCI4 serial
transmission. When this bit is cleared to 0, the TERE
flag in SCSR4 is fixed to 1. When transmit data is
written to TDR4 while this bit is set to 1, the TDRE flag
in SCSR4 is automatically cleared to 0 and serial data
transmission is started.
0: Transmission disabled (SO4 pin functions as I/O
port)
1: Transmission enabled (SO4 pin functions as
transmit data pin)
0 RE 0 R/W Receive Enable
Enables or disables start of the SCI4 serial reception.
Note that the RDRF and ORER flags in SCSR4 are not
affected even if this bit is cleared to 0, and retain their
previous state. Serial data reception is started when
the synchronous clock input is detected while this bit is
set to 1 (when an external clock is selected). When an
internal clock is selected, the synchronous clock is
output and serial data reception is started.
0: Reception disabled (SI4 pin functions as I/O port)
1: Reception enabled (SI4 pin functions as receive data
pin)