Datasheet

Section 18 Serial Communication Interface 4 (SCI4)
Rev. 2.00 Jul. 04, 2007 Page 419 of 692
REJ09B0309-0200
Bit Bit Name
Initial
Value
R/W Description
5 ORER 0 R/(W)* Overrun Error
Indicates that an overrun error occurs during reception
and then abnormal termination occurs. In transfer
mode, the output level of the SO4 pin is fixed to low
while this flag is set to 1. When the RE bit in SCR4 is
cleared to 0, the ORER flag is not affected and retains
its previous state. When RDR4 retains the receive data
it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with the ORER flag set to 1, and
transmission cannot be continued either.
[Setting condition]
• Next serial reception is completed while RDRF = 1
[Clearing condition]
• Writing of 0 to bit ORER after reading ORER = 1
4 TEND 0 R/(W)* Transmit End
Indicates that the TDRE flag has been set to 1 at
transmission of the last bit of transmit data.
[Setting condition]
• TDRE = 1 at transmission of the last bit of transmit
data
[Clearing conditions]
• Writing of 0 to bit to TEND after reading TEND = 1
• Data is written to TDR4 with an instruction
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
0
0
0
R/W
R/W
R/W
R/W
Clock Source Select and Pin Function
Select the clock source to be supplied and set the
input/output for the SCK4 pin. The prescaler division
ratio and transfer clock cycle when an internal clock is
selected are shown in table 18.2. When an external
clock is selected, the external clock cycle should be at
least 4/φ.
Note: * Only 0 can be written to clear the flag.