Datasheet

Section 18 Serial Communication Interface 4 (SCI4)
Rev. 2.00 Jul. 04, 2007 Page 431 of 692
REJ09B0309-0200
Number of transfer
RDRF
Data 1 Data 2 Data 3
Frame 1 Frame 2 Frame 3
(A)
RDR4
(B)
RDR4 read
At the timing of (A), data 1 is read.
At the timing of (B), data 2 is read.
Data 1 Data 2
RDR4 read
Figure 18.9 Relationship between Reading RDR4 and RDRF
In this case, RDR4 must be read only once after confirming RDRF = 1. If reading RDR4 twice or
more, store the read data in the RAM, and use the stored data. In addition, there should be a
margin from the timing of reading RDR4 to completion of the next frame reception (reading
RDR4 should be completed before the bit 7 transfer).
18.6.4 SCK4 Output Waveform when Internal Clock of φ/2 is Selected
When the internal clock of φ/2 is selected by the CKS3 to CKS0 bits in SCSR4 and continuous
transmission or reception is performed, one pulse of high period is lengthened after eight pulses of
the clock has been output as shown in figure 18.10.
SO4/SI4 Bit0 Bit1 Bit2 Bit0 Bit1 Bit2Bit3 Bit4 Bit5 Bit6 Bit7
SCK4
Figure 18.10 Transfer Format when Internal Clock of φ/2 is Selected