Datasheet

Section 20 A/D Converter
Rev. 2.00 Jul. 04, 2007 Page 444 of 692
REJ09B0309-0200
20.3.1 A/D Result Register (ADRR)
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in
the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, but the ADRR value
during A/D conversion is undefined. After A/D conversion is completed, the conversion result is
stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial
value of ADRR is undefined.
ADRR should be read in word size.
20.3.2 A/D Mode Register (AMR)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Bit Bit Name
Initial
Value
R/W Description
7  0  Reserved
This bit is always read as 0 and cannot be modified.
6 TRGE 0 R/W External Trigger Select
Enables or disables the A/D conversion start by the
external trigger input.
0: Disables the A/D conversion start by the external
trigger input.
1: Starts A/D conversion at the rising or falling edge of
the ADTRG pin
The edge of the ADTRG pin is selected by the
ADTRGNEG bit in IEGR.
5
4
CKS1
CKS0
0
0
R/W
R/W
Clock Select
Selects the clock source for A/D conversion.
00: φ/8 (conversion time = 124 states (max.)
(basic clock = φ))
01: φ/4 (conversion time = 62 states (max.)
(basic clock = φ))
10: φ/2 (conversion time = 31 states (max.)
(basic clock = φ))
11: Not selectable (use prohibited)