Datasheet

Section 21 LCD Controller/Driver
Rev. 2.00 Jul. 04, 2007 Page 474 of 692
REJ09B0309-0200
Notes: 1. Power supply might be insufficient when a large panel is driven. In this case, use Vcc
for power supply, or use an external power supply circuit.
2. Do not use a polarized capacitance such as an electrolytic capacitor for connection
between the C1 pin and C2 pin.
3. A 3-V constant-voltage power supply circuit is turned on by SUSP bit regardless of the
setting of the PSW bit.
4. The step-up circuit output voltage in the initial state is different in an individual device
according to the manufacturing difference.
Please set and adjust LCD trimming register (LTRMR) of each individual device.
C1
C2
V2
V1
C
C
C: 0.1 µF
CC
V3
Figure 21.9 Capacitance Connection when Using 3-V Constant-Voltage
Power Supply Circuit
21.4.4 Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
21.6.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φ
W
, φ
W
/2, or φ
W
/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. The subclock can be turned on or off by setting the 32KSTOP bit in
the SUB32k control register (SUB32CR). When it is turned off, display will halt. Since there is a
possibility that a direct current will be applied to the LCD panel in this case, it is essential to
ensure that the subclock is turned on and φ
W
, φ
W
/2, or φ
W
/4 is selected.
In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0
must be modified to ensure that the frame frequency does not change.