Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 482 of 692
REJ09B0309-0200
22.3 Register Descriptions
The I
2
C bus interface 2 has the following registers.
• I
2
C bus control register 1 (ICCR1)
• I
2
C bus control register 2 (ICCR2)
• I
2
C bus mode register (ICMR)
• I
2
C bus interrupt enable register (ICIER)
• I
2
C bus status register (ICSR)
• Slave address register (SAR)
• I
2
C bus transmit data register (ICDRT)
• I
2
C bus receive data register (ICDRR)
• I
2
C bus shift register (ICDRS)
22.3.1 I
2
C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I
2
C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name
Initial
Value
R/W Description
7 ICE 0 R/W I
2
C Bus Interface 2 Enable
0: This module is halted. (SCL and SDA pins are set to
the port/serial function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6 RCVD 0 R/W Reception Disable
This bit enables or disables the next operation when
TRS is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception