Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 485 of 692
REJ09B0309-0200
22.3.2 I
2
C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, handles the SDA pin, monitors the SCL pin, and controls reset
in the control part of the I
2
C bus interface 2.
Bit Bit Name
Initial
Value
R/W Description
7 BBSY 0 R/W Bus Busy
This bit enables to confirm whether the I
2
C bus is
occupied or released and to issue start/stop conditions
in master mode. This bit has no functional role when the
clock synchronous serial format is selected. When the
I
2
C bus format is selected, this bit is set to 1 when the
SDA level changes from high to low under the condition
of SCL = high, assuming that the start condition has
been issued. This bit is cleared to 0 when the SDA level
changes from low to high under the condition of SCL =
high, assuming that the stop condition has been issued.
Write 1 to BBSY and 0 to SCP to issue a start condition.
The same procedure also applies to re-transmitting a
start condition. Write 0 in BBSY and 0 in SCP to issue a
stop condition. To issue start/stop conditions, use the
MOV instruction.
6 SCP 1 R/W Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
5 SDAO 1 R/W SDA Output Value Control
This bit is used with SDAOP when modifying output
level of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).