Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 491 of 692
REJ09B0309-0200
22.3.5 I
2
C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name
Initial
Value
R/W Description
7 TDRE 0 R/(W)* Transmit Data Register Empty
[Setting conditions]
• Data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• TRS is set
• A start condition (including re-transfer) has been
issued
• Transmit mode is entered from receive mode in
slave mode
[Clearing conditions]
• Writing of 0 to bit TDRE after reading TDRE = 1
• Data is written to ICDRT with an instruction
6 TEND 0 R/(W)* Transmit End
[Setting conditions]
• The ninth clock of SCL rises with the I
2
C bus format
while the TDRE flag is 1
• The final bit of transmit frame is sent with the clock
synchronous serial format
[Clearing conditions]
• Writing of 0 to bit TEND after reading TEND = 1
• Data is written to ICDRT with an instruction
5 RDRF 0 R/(W)* Receive Data Register Full
[Setting condition]
• A receive data is transferred from ICDRS to ICDRR
[Clearing conditions]
• Writing of 0 to bit RDRF after reading RDRF = 1
• ICDRR is read with an instruction