Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 494 of 692
REJ09B0309-0200
22.3.6 Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I
2
C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Bit Bit Name
Initial
Value
R/W Description
7 to 1 SVA6 to
SVA0
All 0 R/W Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I
2
C bus.
0 FS 0 R/W Format Select
0: I
2
C bus format is selected.
1: Clock synchronous serial format is selected.
22.3.7 I
2
C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and
when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF.
22.3.8 I
2
C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is
H'FF.
22.3.9 I
2
C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.