Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 495 of 692
REJ09B0309-0200
22.4 Operation
The I
2
C bus interface 2 can communicate either in I
2
C bus mode or clock synchronous serial mode
by setting the FS bit in the slave address register (SAR).
22.4.1 I
2
C Bus Format
Figure 22.3 shows the I
2
C bus formats. Figure 22.4 shows the I
2
C bus timing. The first frame
following a start condition always consists of 8 bits.
S SLA R/W A DATA A A/A P
1111n7
1
m
(a) I
2
C bus format (FS = 0)
(b) I
2
C bus format (Start condition retransmission, FS = 0)
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
S SLA R/W A DATA
111n17
1
m1
S SLA R/W A DATA A/A P
111n27
1
m2
111
A/A
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
11
Figure 22.3 I
2
C Bus Formats
SDA
SCL
S
1 to 7
SLA
8
R/W
9
A
1 to 7
DATA
8 9 1 to 7 8 9
A DATA P
A
Figure 22.4 I
2
C Bus Timing