Datasheet

Section 22 I
2
C Bus Interface 2 (IIC2)
Rev. 2.00 Jul. 04, 2007 Page 512 of 692
REJ09B0309-0200
22.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 22.3 shows the contents of
each interrupt request.
Table 22.3 Interrupt Requests
Interrupt Request Abbreviation Interrupt Condition I
2
C Mode
Clock
Synchronous
Mode
Transmit data empty TXI (TDRE=1)
•
(TIE=1) Available Available
Transmit end TEI (TEND=1)
•
(TEIE=1) Available Available
Receive data full RXI (RDRF=1)
•
(RIE=1) Available Available
STOP recognition STPI (STOP=1)
•
(STIE=1) Available Not available
NACK receive Available Not available
Arbitration
lost/overrun
NAKI {(NACKF=1)+(AL=1)}
•
(NAKIE=1)
Available Available
When interrupt conditions described in table 22.3 are 1 and the I bit in CCR is 0, the CPU
executes interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.