Datasheet

Section 24 Address Break
Rev. 2.00 Jul. 04, 2007 Page 520 of 692
REJ09B0309-0200
24.1 Register Descriptions
The address break has the following registers.
• Address break control register 2 (ABRKCR2)
• Address break status register 2 (ABRKSR2)
• Break address register 2 (BAR2E, BAR2H, BAR2L)
• Break data register 2 (BDR2H, BDR2L)
24.1.1 Address Break Control Register 2 (ABRKCR2)
ABRKCR2 sets address break conditions.
Bit Bit Name
Initial
Value
R/W Description
7 RTINTE2 1 R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
5
CSEL21
CSEL20
0
0
R/W
R/W
Condition Select 1 and 0
These bits set address break conditions.
00: Instruction execution cycle (no data comparison)
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
4
3
2
ACMP22
ACMP21
ACMP20
0
0
0
R/W
R/W
R/W
Address Compare Condition Select 2 to 0
These bits set the comparison condition between the
address set in BAR2 and the internal address bus.
000: Compares all of 24-bit addresses
001: Compares upper 20-bit addresses
010: Compares upper 16-bit addresses
011: Compares upper 12-bit addresses
100: Compares upper 8-bit addresses
101: Compares upper 4-bit addresses
11x: Setting prohibited