Datasheet

Rev. 2.00 Jul. 04, 2007 Page 665 of 692
REJ09B0309-0200
Main Revisions and Additions in this Edition
Item Page Revisions (See Manual for Details)
Section 1 Overview
1.1 Features
• Compact package
2 The description on the package, LGA-113, is deleted.
Figure 1.2 Pin Assignment of
H8/38099 Group (PLQP0100KB-
A)
4 Modified
Figure 1.3 Pin Assignment of
H8/38099 Group (PTLG0113JA-
A)
Deleted
Table 1.1 PTLG0113JA-A Pin
Correspondence
Deleted
Table 1.1 Pin Functions 5 to 10 The column on the PTLG0113JA-A is deleted.
Section 2 CPU
2.8.3 Bit-Manipulation Instruction
42
The programs for executing the instruction are modified.
Section 3 Exception Handling
3.2.1 Reset Exception Handling
49 Modified
:
2. The reset exception handling vector address (H'000000 to
H'000003) is read and transferred to the PC, and then
program execution starts from the address indicated by the
PC.
Section 4 Interrupt Controller
4.5 Interrupt Exception Handling
Vector Table
73 Deleted
Table 4.2 shows interrupt exception handling sources, vector
addresses, and interrupt priorities. For default
priorities, the
lower the vector number, the higher the mask level. Priorities
within a module are fixed. Interrupt mask levels other than NMI
and address break can be modified by IPR.
4.6 Operation 77 Modified
:
2. With referring to the INTM1 and INTM0 bits in INTM and
the I bit in CCR, control the following.
 The interrupt request is held pending when the I bit is
set to 1.
 When the I bit is cleared to 0 and INTM1 bit is set to 1,
interrupts with mask level 1 or less are held pending.