Datasheet

Rev. 2.00 Jul. 04, 2007 Page 673 of 692
REJ09B0309-0200
Item Page Revisions (See Manual for Details)
6.3.3 Direct Transition from
Active (Medium-Speed) Mode to
Active (High-Speed) Mode
120 Added
When a SLEEP instruction is executed in active (medium-speed)
mode while the SSBY and LSON bits in SYSCR1 are cleared to
0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in
SYSCR2 is set to 1, a transition is made to active (high-speed)
mode via sleep mode.
The time from the start of SLEEP instruction execution to the end
of interrupt exception handling (the direct transition time) is
calculated by equation (3).
:
Example: When φosc/8 is selected as the CPU operating clock
before the transition
Direct transition time = (2 + 1) × 8tosc + 14 × 1tosc = 38tosc
For the legend of symbols used above, refer to section 26,
Electrical Characteristics.
6.3.4 Direct Transition from
Active (Medium-Speed) Mode to
Subactive Mode
121 Added
When a SLEEP instruction is executed in active (medium-speed)
mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set
to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made
to subactive mode via watch mode.
The time from the start of SLEEP instruction execution to the end
of interrupt exception handling (the direct transition time) is
calculated by equation (4).
:
Example: When φosc/8 and φw/8 are selected as the CPU
operating clock before and after the transition, respectively
Direct transition time = (2 + 1) × 8tosc + 14 × 8tw = 24tosc +
112tw
For the legend of symbols used above, refer to section 26,
Electrical Characteristics.