Datasheet

Rev. 2.00 Jul. 04, 2007 Page 682 of 692
REJ09B0309-0200
Item Page Revisions (See Manual for Details)
Figure 12.4 TMOFH/TMOFL
Output Timing
245 Modified
Figure 12.5 TCF Clear Timing 245 Added
Figure 12.6 Compare Match
Flag Set Timing
246 Added
12.6.1 16-Bit Timer Mode 248 Modified
… However, if the written data and the counter value match,
there is a probability of a compare match signal being generated
and not being generated.
12.6.2 8-Bit Timer Mode
(1) TCFH, OCRFH
248 Modified
… However, even if the written data and the counter value
match, there is a probability of a compare match signal being
generated and not being generated.
(2) TCFL, OCRFL 249 Modified
… However, even if the written data and the counter value
match, there is a probability of a compare match signal being
generated and not being generated.
12.6.4 Timer Counter (TCF)
Read/Write
251 Modified
When the internal clock φ
W
/4 is selected as the counter input
clock in active (high-speed, medium-speed) mode, normal write
is not performed on TCF. And when reading TCF, as the system
clock and internal clock are mutually asynchronous, TCF
synchronizes with synchronization circuit. This results in a
maximum TCF read value error of ±1.
When reading or writing TCF in active (high
-speed, medium-
speed) mode is needed, select the input clock except for φ
W
/4
before read/write is performed.
Section 13 Timer G
Figure 13.4 Input Capture Input
Timing (without Noise
Cancellation Function)
262 Modified
Figure 13.6 Timing of Input
Capture by Input Capture Input
263 Modified
Figure 13.7 TCG Clear Timing 264 Modified