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Preface The H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group are a highperformance single-chip microcomputers that integrate peripheral functions necessary for system configuration with an H8/300L CPU core. The on-chip peripheral functions include ROM, RAM, six timers, 14-bit PWM, a serial communication interface (SCI), an A/D converter, LCD controller/driver, and I/O ports, providing an ideal configuration as a microcomputer for embedding in sophisticated control systems.
Notes: The following limitations apply when using the on-chip emulator for program development and debugging. 1. Pin P24 is reserved for use exclusively by the on-chip emulator and cannot be used for other operations. 2. Pins P25, P26, and P27 cannot be used. In order to use these pins it is necessary to install additional hardware on the user board. 3. The address area from H'E000 to H'EFFF is used by the on-chip emulator and therefore cannot be accessed by the user. 4.
Application Note: Manual Title Document No. H8/300L Series Application Note ADE-502-065 Rev. 6.
Rev. 6.
Main Revisions for this Edition Item Page Revision (See Manual for Details) All “Under development” indication deleted from H8/38447 Group Preface iv Added Notes: 6. During a break, the watchdog timer continues to operate. Therefore, an internal reset is generated if an overflow occurs during the break. 1.3.2 Pin Functions 33 Table amended Table 1.6 Pin Functions 8.3.1 Overview Pin No.
Item Page Revision (See Manual for Details) 8.15.1 The Management of the Un-Use Terminal 256 Description amended • If an unused pin is an output pin, handle it in one of the following ways: Set the output of the unused pin to high and pull it up to VCC with an external resistor of approximately 100 kΩ. Set the output of the unused pin to low and pull it down to Vss with an external resistor of approximately 100 kΩ. 15.8.2 DC Characteristics 519, 525 Table 15.
Item Page Appendix D Port 660 States in the Different Processing States Table D.1 Port States Overview Revision (See Manual for Details) Table and notes amended Port Reset P27 to P20 Highimpedance*3 Notes: 1. High level output when MOS pull-up is in on state. 2. Reset output from P32 pin only (H8/3847R Group and H8/3847S Group). 3. On-chip pull-up MOS turns on for pin P24 only (F-ZTAT Version of the H8/38347 Group and H8/38447 Group). Rev. 6.
Rev. 6.
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 7 Pin Arrangement and Functions......................................................................
2.8 2.9 2.7.3 Program Halt State............................................................................................... 2.7.4 Exception-Handling State .................................................................................... Memory Map .................................................................................................................... 2.8.1 Memory Map .......................................................................................................
Section 5 Power-Down Modes ........................................................................................ 131 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Overview........................................................................................................................... 5.1.1 System Control Registers..................................................................................... Sleep Mode .........................................................................................
6.1.1 Block Diagram ..................................................................................................... PROM Mode (H8/3847R)................................................................................................. 6.2.1 Setting to PROM Mode ....................................................................................... 6.2.2 Socket Adapter Pin Arrangement and Memory Map........................................... 6.3 Programming (H8/3847R) ...................................
6.11 Power-Down States for Flash Memory............................................................................. 200 Section 7 RAM ..................................................................................................................... 201 7.1 Overview........................................................................................................................... 201 7.1.1 Block Diagram .............................................................................................
8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.7.4 Pin States.............................................................................................................. 8.7.5 MOS Input Pull-Up.............................................................................................. Port 7................................................................................................................................. 8.8.1 Overview.......................................................................
9.3 9.4 9.5 9.6 9.7 9.2.3 Timer Operation................................................................................................... 9.2.4 Timer A Operation States .................................................................................... 9.2.5 Application Note.................................................................................................. Timer C .........................................................................................................................
10.2.4 Operation in SSB Mode ....................................................................................... 10.2.5 Interrupt Source ................................................................................................... 10.2.6 Application Notes ................................................................................................ 10.3 SCI3 .................................................................................................................................. 10.3.
12.5 Typical Use ....................................................................................................................... 12.6 Application Notes ............................................................................................................. 12.6.1 Application Notes ................................................................................................ 12.6.2 Permissible Signal Source Impedance ................................................................. 12.6.
15.2.5 LCD Characteristics............................................................................................. 15.3 H8/3847R Group Absolute Maximum Ratings (Wide-range Specification) .................... 15.4 H8/3847R Electrical Characteristics (Wide-range Specification)..................................... 15.4.1 Power Supply Voltage and Operating Range....................................................... 15.4.2 DC Characteristics .................................................................
C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 Block Diagrams of Port 3.................................................................................................. Block Diagrams of Port 4.................................................................................................. Block Diagram of Port 5 ................................................................................................... Block Diagram of Port 6 ..........................................................................
Figures Section 1 Overview Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group) ................................ Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group) ................................. Figure 1.2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View) ................ Figure 1.3 Pin Arrangement (FP-100A: Top View) ........................................................... Figure 1.4 Bonding Pad Location Diagram of H8/3847R Group (Mask ROM Version) (Top View) ......
Figure 2.17 Figure 2.18 Data Size and Number of States for Access to and from On-Chip Peripheral Modules ............................................................................................................. 84 Timer Configuration Example........................................................................... 86 Section 3 Exception Handling Figure 3.1 Reset Sequence .................................................................................................. Figure 3.
Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10 Figure 6.11 Figure 6.12 Figure 6.13 Figure 6.14 Figure 6.15 Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20 High-Speed, High-Reliability Programming Flow Chart .................................. PROM Write/Verify Timing.............................................................................. Recommended Screening Procedure .................................................................
Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 9.14 Figure 9.15 Figure 9.16 Figure 9.17 Figure 9.18 Figure 9.19 Figure 9.20 Figure 9.21 Block Diagram of Timer C ................................................................................ Block Diagram of Timer F ................................................................................ Write Access to TCR (CPU → TCF) ...................................
Figure 10.12 Figure 10.13 Figure 10.14 Figure 10.15 Figure 10.16 Figure 10.17 Figure 10.18 Figure 10.19 Figure 10.20 Figure 10.21 Figure 10.22 Figure 10.23 Figure 10.24 Figure 10.25 Figure 10.26 Figure 10.27 Example of Operation when Transmitting in Asynchronous Mode (8-bit data, parity, 1 stop bit) ............................................................................. Example of Data Reception Flowchart (Asynchronous Mode) .........................
Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty) ............. LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) ............. LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) ............. LCD RAM Map with Segments Not Externally Expanded (Static Mode) ........
Figure C.1 (d) Port 1 Block Diagram (Pin P10)......................................................................... 633 Figure C.2 (a-1) Port 2 Block Diagram (Pins P27 to P23, Not Including P24 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group).................................................. 634 Figure C.2 (a-2) Port 2 Block Diagram (Pin P24 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group).......................................................................................
Figure G.4 Chip Sectional Figure ........................................................................................ 673 Appendix H Form of Bonding Pads Figure H.1 Bonding Pad Form............................................................................................. 674 Figure H.2 Bonding Pad Form............................................................................................. 675 Figure H.3 Bonding Pad Form...........................................................................
Tables Section 1 Overview Table 1.1 Features .................................................................................................................. 2 Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) .................. 13 Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) .................. 18 Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447......................... 23 Table 1.
Section 6 ROM Table 6.1 Setting to PROM Mode.......................................................................................... 157 Table 6.2 Socket Adapter ....................................................................................................... 157 Table 6.3 Mode Selection in PROM Mode (H8/3847R)........................................................ 160 Table 6.4 DC Characteristics..................................................................................................
Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Table 8.19 Table 8.20 Table 8.21 Table 8.22 Table 8.23 Table 8.24 Table 8.25 Table 8.26 Table 8.27 Table 8.28 Table 8.29 Table 8.30 Table 8.31 Table 8.32 Table 8.33 Table 8.34 Port 4 Pin States ..................................................................................................... Port 5 Registers ...................................................................................................... Port 5 Pin Functions ........
Table 9.16 Table 9.17 Table 9.18 Table 9.19 Table 9.20 Table 9.21 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching, and Conditions for Their Occurrence ..................................................................... 309 Watchdog Timer Registers ..................................................................................... 313 Watchdog Timer Operation States ......................................................................... 319 Pin Configuration ...........
Section 13 LCD Controller/Driver Table 13.1 Pin Configuration ................................................................................................... Table 13.2 LCD Controller/Driver Registers ........................................................................... Table 13.3 Output Levels ......................................................................................................... Table 13.4 Power-Down Modes and Display Operation...................................................
Appendix A CPU Instruction Set Table A.1 Instruction Set ........................................................................................................ Table A.2 Operation Code Map .............................................................................................. Table A.3 Number of Cycles in Each Instruction ................................................................... Table A.4 Number of Cycles in Each Instruction ................................................................
Rev. 6.
Section 1 Overview Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group comprise single-chip microcomputers equipped with an LCD (liquid crystal display) controller/driver.
Section 1 Overview Table 1.1 Features Item Description CPU High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • • • Interrupts Clock pulse generators Operating speed Max. operating speed: 8 MHz Add/subtract: 0.25 µs (operating at 8 MHz) Multiply/divide: 1.75 µs (operating at 8 MHz) Can run on 32.768 kHz or 38.
Section 1 Overview Item Description Power-down modes • Seven power-down modes • Sleep (high-speed) mode • Sleep (medium-speed) mode • Standby mode • Watch mode • Subsleep mode • Subactive mode • Active (medium-speed) mode Memory I/O ports Large on-chip memory • H8/3842R, H8/38342, H8/38442: 16-Kbyte ROM, 1-Kbyte RAM • H8/3843R, H8/38343, H8/38443: 24-Kbyte ROM, 1-Kbyte RAM • H8/3844R, H8/3844S, H8/38344, H8/38444: 32-Kbyte ROM, 2-Kbyte RAM • H8/3845R, H8/3845S, H8/38345, H8/38445
Section 1 Overview Item Description Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ)* and four clock signals divided from the watch clock (φw)* • Asynchronous event counter: 16-bit timer • • • • Timer C: 8-bit timer Count-up/down timer with selection of seven internal clock signals or event input from external pin Auto-reloading Timer F: 16-bit timer Can be used as two independent 8-bit ti
Section 1 Overview Item Description A/D converter Successive approximations using a resistance ladder LCD controller/driver • 12-channel analog input pins • Conversion time: 31/φ or 62/φ per channel LCD controller/driver equipped with a maximum of 40 segment pins and four common pins • Choice of four duty cycles (static, 1/2, 1/3, or 1/4) • Segment pins can be switched to general-purpose port function in 8-bit units Rev. 6.
Section 1 Overview Item Description Product lineup Mask ROM Version ZTAT Version F-ZTAT Version HD6433847R HD6433847S HD64338347 HD64338447 HD6473847R HD64F38347 HD64F38447 FP-100A (H8/3847R only) FP-100B TFP-100B TFP-100G Die 60 K/2 K HD6433846R HD6433846S HD64338346 HD64338446 — — FP-100A (H8/3846R only) FP-100B TFP-100B TFP-100G Die 48 K/2 K HD6433845R HD6433845S HD64338345 HD64338445 — — FP-100A (H8/3845R only) FP-100B TFP-100B TFP-100G Die 40 K/2 K HD6433844R HD6433844S HD64338344
Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 (1) shows a block diagram of the H8/3847R Group and H8/3847S Group.
LCD power supply RES TEST VSS VSS VCC CVCC X1 X2 Sub clock OSC Port A Port 9 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 14-bit PWM Timer G LCD controller/driver WDT A/D (10-bit) Asynchronous counter PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 Port B AVSS Port 8 Serial communication interface 3-2 Timer F AVCC Port 7 System clock OSC Port 2 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 Port 6 P50/
Section 1 Overview 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The pin arrangements of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group are shown in figures 1.2 and 1.3 (figure 1.3 only applies to the H8/3847R Group). The bonding pad location diagram of the H8/3847R Group (Mask ROM version) is shown in figure 1.4. The bonding pad coordinates of the H8/3847R Group (Mask ROM version) are given in table 1.2.
P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Section 1 Overview V3 PB5/AN5 93 33 VSS PB6/AN6 94 32 CVCC (VCC in the H8/3847S) PB7/AN7 95 31 P37/AEVL PC0/AN8 96 30 P36
23 24 25 26 27 28 29 30 P25 P26 P27 P30/PWM P31/UD P32/RESO P33/SCK31 19 P20/SCK1 P24 18 RES 22 17 TEST P23 16 OSC1 21 15 OSC2 P22/SO1 14 VSS 20 13 X2 P21/SI1 12 X1 9 P15/IRQ1/TMIC 11 8 P14/IRQ4/ADTRG P17/IRQ3/TMIF 7 P13/TMIG 10 6 P12/TMOFH P16/IRQ2 5 P11/TMOFL 3 AVSS 4 2 PC3/AN11 P10/TMOW 1 PC2/AN10 P92/SEG35 P91/SEG34 P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SE
Section 1 Overview 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 8584 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Y X (0, 0) Type code 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 52 51 43 44 45 46 47 48 49 50 : NC Pad Chip size : 6.10mm × 6.23mm Voltage level on the back of the chip : GND Figure 1.
Section 1 Overview Table 1.2 Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) 95 PB7/AN7 -1532 2931 96 PC0/AN8 -1704 2931 97 PC1/AN9 -1876 2931 98 PC2/AN10 -2048 2931 99 PC3/AN11 -2658 2931 100 AVSS -2866 2931 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads. Rev. 6.
Section 1 Overview 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Type code Y X (0, 0) Base type code 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 : NC Pad Chip size : 3.55mm × 3.45mm Voltage level on the back of the chip : GND Figure 1.
Section 1 Overview Table 1.3 Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) 95 PB7/AN7 -767 1605 96 PC0/AN8 -879 1605 97 PC1/AN9 -991 1605 98 PC2/AN10 -1103 1605 99 PC3/AN11 -1290 1605 100 AVSS -1523 1605 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads. Rev. 6.
Section 1 Overview 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 Type code 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 72 71 70 69 68 Y 67 (0, 0) 66 65 64 63 62 61 60 X 59 58 57 56 24 25 26 55 54 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 52 : NC Pad Chip size : 4.35mm × 4.83mm Voltage level on the back of the chip : GND Figure 1.
Section 1 Overview Table 1.4 Bonding Pad Coordinates of HCD64F38347 and HCD64F38447 Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) 95 PB6/AN6 -996 2295 96 PB7/AN7 -1102 2295 97 PC0/AN8 -1208 2295 98 PC1/AN9 -1313 2295 99 PC2/AN10 -1419 2295 100 PC3/AN11 -1530 2295 AVSS -1777 2295 101 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.
Section 1 Overview Base type code 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 Type code 76 75 74 1 73 2 72 3 4 5 71 6 7 8 9 10 68 70 69 67 Y 66 65 11 12 13 14 15 64 63 (0, 0) 62 X 61 16 17 18 19 20 21 22 23 24 60 25 52 59 58 57 56 55 54 53 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Chip size : 3.55mm × 3.77mm Voltage level on the back of the chip : GND Figure 1.
Section 1 Overview Table 1.5 Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version) and H8/38447 Group (Mask ROM Version) Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No.
Section 1 Overview Coordinates* Pad No. Pad Name X (µm) Y (µm) 95 PB7/AN7 -766 1767 96 PC0/AN8 -872 1767 97 PC1/AN9 -978 1767 98 PC2/AN10 -1084 1767 99 PC3/AN11 -1190 1767 100 AVSS -1629 1767 Note: * These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The home-point position is the chip’s center and the center is located at half the distance between the upper and lower pads and left and right pads.
Section 1 Overview 1.3.2 Pin Functions Table 1.6 outlines the pin functions of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group. Table 1.6 Pin Functions Pin No. Type Symbol FP-100B TFP-100B TFP-100G Power source pins VCC CVCC 38 32 41 35 Input Power supply: All VCC pins should be connected to the system power supply. See section 14, Power Supply Circuit, for a CVcc pin (Vcc pin in the H8/3847S Group).
Section 1 Overview Pin No. FP-100B TFP-100B TFP-100G FP-100A I/O Name and Functions Clock pins OSC1 13 16 Input OSC2 12 15 Output These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. X1 9 12 Input X2 10 13 These pins connect to a 32.768 kHz or 38.4 kHz crystal oscillator. Output See section 4, Clock Pulse Generators, for a typical connection diagram.
Section 1 Overview Pin No. FP-100B TFP-100B TFP-100G FP-100A I/O Name and Functions 1 4 Output Clock output: This is an output pin for waveforms generated by the timer A output circuit. AEVL AEVH 31 30 34 33 Input Asynchronous event counter event input: This is an event input pin for input to the asynchronous event counter. TMIC 6 9 Input Timer C event input: This is an event input pin for input to the timer C counter.
Section 1 Overview Pin No. Type Symbol I/O ports FP-100B TFP-100B TFP-100G FP-100A I/O Name and Functions PA3 to PA0 39 to 42 42 to 45 I/O Port A: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). P17 to P10 8 to 1 11 to 4 I/O Port 1: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1). P27 to P20 23 to 16 26 to 19 I/O Port 2: This is an 8-bit I/O port.
Section 1 Overview Pin No. Type Symbol I/O ports FP-100A I/O Name and Functions P87 to P80 74 to 67 77 to 70 I/O Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). P97 to P90 82 to 75 85 to 78 I/O Port 9: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9). 17 20 Input SCI1 receive data input: This is the SCI1 data input pin.
Section 1 Overview Pin No. Type Symbol LCD COM4 to controller/ COM1 driver SEG40 to SEG1 CL1 FP-100B TFP-100B TFP-100G FP-100A I/O Name and Functions 39 to 42 42 to 45 Output LCD common output: These are the LCD common output pins. 82 to 43 85 to 46 Output LCD segment output: These are the LCD segment output pins. 82 85 Output LCD latch clock: This is the display data latch clock output pin for external expansion of the segment.
Section 1 Overview Rev. 6.
Section 2 CPU Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below.
Section 2 CPU • Low-power operation modes SLEEP instruction for transfer to low-power operation Note: * These values are at φ = 8 MHz. 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. Rev. 6.
Section 2 CPU 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Section 2 CPU 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Section 2 CPU ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6—User Bit (U): Can be used freely by the user. Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.
Section 2 CPU 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 2.
Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. The same applies to instruction codes.
Section 2 CPU 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No.
Section 2 CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
Section 2 CPU The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.
Rev. 6.00 Aug 04, 2006 page 50 of 680 REJ09B0145-0600 4 3 2 rm op 7 6 rm 4 3 4 3 rn 0 0 op disp 7 6 rm op 7 6 rm 4 3 4 3 0 0 15 op 7 6 rm 4 3 0 Register indirect with pre-decrement, @–Rn 15 Register indirect with post-increment, @Rn+ 15 Register indirect with displacement, @(d:16, Rn) 15 Register indirect, @Rn op 8 7 Register direct, Rn 1 15 Addressing Mode and Instruction Format No.
7 6 5 No.. op op IMM op 8 7 abs op 8 7 IMM abs 15 op 8 7 disp Program-counter relative @(d:8, PC) 15 #xx:16 15 Immediate #xx:8 15 @aa:16 15 Absolute address @aa:8 Addressing Mode and Instruction Format 0 0 0 0 0 PC contents Sign extension 15 disp 0 15 15 H'FF 8 7 Effective Address (EA) 0 0 15 0 Operand is 1- or 2-byte immediate data Effective Address Calculation Method Section 2 CPU Rev. 6.
Legend: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address op 8 7 abs Memory indirect, @@aa:8 8 15 Addressing Mode and Instruction Format No. 0 15 8 7 abs Memory contents (16 bits) H'00 0 Effective Address Calculation Method 15 Effective Address (EA) 0 Section 2 CPU Rev. 6.
Section 2 CPU 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.
Section 2 CPU Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), Destination operand (EAs), Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logica
Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+ addressing modes are available for word data.
Section 2 CPU 15 8 7 0 op rm 15 8 rn 0 rm 8 Rm→Rn 7 op 15 MOV rn @Rm←→Rn 7 0 op rm rn @(d:16, Rm)←→Rn disp 15 8 7 0 op rm 15 8 op 7 0 rn 15 @Rm+→Rn, or Rn→ @-Rm rn abs 8 @aa:8←→Rn 7 0 op rn @aa:16←→Rn abs 15 8 op 7 0 rn 15 IMM 8 #xx:8→Rn 7 0 op rn #xx:16→Rn IMM 15 8 7 op 0 1 1 1 rn Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function ADD SUB B/W Rd ± Rs → Rd, Rd + #IMM → Rd ADDX SUBX B INC DEC B ADDS SUBS W DAA DAS B MULXU B Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.
Section 2 CPU 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.
Section 2 CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory to 0.
Section 2 CPU Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C ⊕ [~( of )] → C XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Copies a specified bit in a general register or memory to the C flag.
Section 2 CPU BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn Operand: register direct (Rn) Bit No.: register direct (Rm) rn 7 op 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit No.: op 15 8 15 8 7 0 7 abs IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit No.
Section 2 CPU BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 IMM 8 7 op op 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) Legend: Operation field op: rm, rn: Register field Absolute address abs: IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont) Rev. 6.
Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if condition cc is true. The branching conditions are given below.
Section 2 CPU 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 op 0 abs 15 8 7 op Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 6.
Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Section 2 CPU 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 7 LDC, STC (Rn) 0 op IMM ANDC, ORC, XORC, LDC (#xx:8) Legend: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.
Section 2 CPU 15 8 7 0 op op Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 6.
Section 2 CPU 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.
Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Section 2 CPU Three-state access to on-chip peripheral modules Bus cycle T1 state T2 state T3 state φ or φ SUB Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) Rev. 6.
Section 2 CPU 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions. Rev. 6.
Section 2 CPU CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Program halt state A state in which some or all of the chip funct
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source occurs Program halt state Interrupt source occurs Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Section 2 CPU 2.8 Memory Map 2.8.1 Memory Map The memory map of the H8/3842R, H8/38342, and H8/38442 is shown in figure 2.16 (1), that of the H8/3843R, H8/38343, and H8/38443 in figure 2.16 (2), that of the H8/3844R, H8/3844S, H8/38344, and H8/38444 in figure 2.16 (3), that of the H8/3845R, H8/3845S, H8/38345, and H8/38445 in figure 2.16 (4), that of the H8/3846R, H8/3846S, H8/38346, and H8/38446 in figure 2.16 (5), and that of the H8/3847R, H8/3847S, H8/38347, and H8/38447 in figure 2.16 (6). Rev. 6.
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 16 Kbytes On-chip ROM (16384 bytes) H'3FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 1024 bytes H'FB7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map Rev. 6.
Section 2 CPU H'0000 H'0029 Interrupt vector area H'002A 24 Kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 H'F75F LCD RAM (32 bytes) Not used H'F780 On-chip RAM 1024 bytes H'FB7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map Rev. 6.
Section 2 CPU HD6433844R (Mask ROM Version) HD6433844S (Mask ROM Version) HD64338344 (Mask ROM Version) HD64338444 (Mask ROM Version) HD64F38344 (Flash Memory Version) HD64F38444 (Flash Memory Version) H'0000 H'0000 Interrupt vector area H'0029 Interrupt vector area H'0029 H'002A 32 Kbytes H'002A 32 Kbytes (32768 bytes) (32768 bytes) On-chip ROM On-chip ROM H'7FFF H'7FFF Not used H'E000 H'EFFF Firmware for on-chip emulator*1 Not used Not used H'F020 H'F02B Internal I/O registers Not us
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 40 Kbytes On-chip ROM (40960 bytes) H'9FFF Not used H'F740 LCD RAM (32 bytes) H'F75F Not used H'F780 On-chip RAM 2048 bytes H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map Rev. 6.
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 48 Kbytes (49152 bytes) On-chip ROM H'BFFF Not used H'F740 H'F75F LCD RAM (32 bytes) Not used H'F780 On-chip RAM 2048 bytes H'FF7F Not used H'FF90 Internal I/O registers (112 bytes) H'FFFF Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map Rev. 6.
Section 2 CPU HD6433847R (Mask ROM Version) HD6433847S (Mask ROM Version) HD64338347 (Mask ROM Version) HD64338447 (Mask ROM Version) HD6473847R (PROM Version) HD64F38347 (Flash Memory Version) HD64F38447 (Flash Memory Version) H'0000 H'0000 Interrupt vector area H'0029 H'0029 H'002A H'002A On-chip ROM H'E000 H'EFFF 61440 bytes Interrupt vector area On-chip ROM 60928 bytes H'EDFF Firmware for on-chip emulator*1 Not used H'F020 H'F02B Internal I/O registers Not used Not used H'F300 H'F6FF
Section 2 CPU 2.9 Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate.
Section 2 CPU Access States Word Byte H'0000 H'0029 Interrupt vector area (42 bytes) H'002A 2 32Kbytes On-chip ROM H'7FFF Not used — — — H'F740 LCD RAM (20 bytes) 2 H'F753 — Not used — — H'F780 On-chip RAM 2 2048 bytes H'FF7F Not used — H'FF90 Internal I/O registers (112 bytes) H'FF98 to H'FF9F H'FFA8 to H'FFAF H'FFFF — — × 2 × 3 × 2 × 3 × 2 Note: The H8/3844R, H8/3844S, H8/38344, and H8/38444 are shown as an example. Figure 2.
Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Section 2 CPU Read Count clock Timer counter Reload Write Timer load register Internal bus Figure 2.18 Timer Configuration Example Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output.
Section 2 CPU [C: After executing BSET] P37 P36 P35 P34 P33 P32 P31 P30 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3.
Section 2 CPU [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). [C: After executing BSET] MOV. B @RAM0, MOV. B R0L, R0L @PDR3 The work area (RAM0) value is written to PDR3.
Section 2 CPU [B: BCLR instruction executed] BSET #0 , @PCR3 The BCLR instruction is executed designating PCR3.
Section 2 CPU [B: BCLR instruction executed] BCLR #0 , The BCLR instruction is executed designating the PCR3 work area (RAM0). @RAM0 [C: After executing BCLR] MOV. B @RAM0, MOV. B R0L, The work area (RAM0) value is written to PCR3.
Section 2 CPU Table 2.13 Registers with Write-Only Bits Register Name Abbr.
Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ← R6 R5 + R4L → ← R6 + R4L • When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
Section 3 Exception Handling Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3847R Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.
Section 3 Exception Handling When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES φ Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16-bit) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3.1 Reset Sequence 3.2.
Section 3 Exception Handling 3.3 Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (IRQ4 to IRQ0, WKP7 to WKP0) and 24 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: • Internal and external interrupts can be masked by the I bit in CCR.
Section 3 Exception Handling Table 3.
Section 3 Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.
Section 3 Exception Handling Bit 3: IRQ3 edge select (IEG3) Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin. Bit 3 IEG3 Description 0 Falling edge of IRQ3 and TMIF pin input is detected 1 Rising edge of IRQ3 and TMIF pin input is detected (initial value) Bit 2: IRQ2 edge select (IEG2) Bit 2 selects the input sensing of pin IRQ2.
Section 3 Exception Handling 2. Interrupt Enable Register 1 (IENR1) Bit 7 6 5 4 3 2 1 0 IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7: Timer A interrupt enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests.
Section 3 Exception Handling Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0) Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests. Bit n IENn Description 0 Disables interrupt requests from pin IRQn 1 Enables interrupt requests from pin IRQn (initial value) (n = 4 to 0) 3.
Section 3 Exception Handling Bit 4: Timer G interrupt enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG Description 0 Disables timer G interrupt requests 1 Enables timer G interrupt requests (initial value) Bit 3: Timer FH interrupt enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Section 3 Exception Handling Bit 0: Asynchronous event counter interrupt enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests. Bit 0 IENEC Description 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests (initial value) For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in section 10.3.2. 4.
Section 3 Exception Handling Bit 6: SCI1 interrupt request flag (IRRS1) Bit 6 IRRS1 Description 0 Clearing condition: When IRRS1 = 1, it is cleared by writing 0 1 Setting condition: When SCI1 completes transfer (initial value) Bit 5: Reserved bit Bit 5 is reserved; it is always read as 1 and cannot be modified.
Section 3 Exception Handling Bit 7: Direct transfer interrupt request flag (IRRDT) Bit 7 IRRDT Description 0 Clearing condition: When IRRDT = 1, it is cleared by writing 0 1 Setting condition: When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2 (initial value) Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD Description 0 Clearing condition: When IRRAD = 1, it is cleared by writing 0 1 Setting condition: When A/D conversion is completed and AD
Section 3 Exception Handling Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH Description 0 Clearing condition: When IRRTFH = 1, it is cleared by writing 0 (initial value) 1 Setting condition: When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode Bit 2: Timer FL interrupt request flag (IRRTFL) Bit 2 IRRTFL Description 0 Clearing condition: When IRRTFL= 1, it is cleared by writing 0 (initial value) 1 Setting condit
Section 3 Exception Handling 6. Wakeup Interrupt Request Register (IWPR) Bit 7 6 5 4 3 2 1 0 IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * All bits can only be written with 0, for flag clearing. IWPR is an 8-bit read/write register containing wakeup interrupt request flags.
Section 3 Exception Handling Bit n: WKPn edge select (WKEGSn) Bit n selects WKPn pin input sensing. Bit n WKEGSn Description 0 WKPn pin falling edge detected 1 WKPn pin rising edge detected (initial value) (n = 7 to 0) 3.3.3 External Interrupts There are 13 external interrupts: IRQ4 to IRQ0 and WKP7 to WKP0. 1. Interrupts WKP7 to WKP0 Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to WKP0.
Section 3 Exception Handling 3.3.4 Internal Interrupts There are 24 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR.
Section 3 Exception Handling Interrupt operation is described as follows. • When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. • When the interrupt controller receives an interrupt request, it sets the interrupt request flag. • From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending.
Section 3 Exception Handling Program execution state IRRI0 = 1 No Yes IEN0 = 1 No Yes IRRI1 = 1 No Yes IEN1 = 1 Yes No IRRI2 = 1 No Yes IEN2 = 1 No Yes IRRDT = 1 No Yes IENDT = 1 Yes No I=0 Yes PC contents saved CCR contents saved I←1 Branch to interrupt handling routine Legend: PC: Program counter CCR: Condition code register I: I bit of CCR Figure 3.3 Flow Up to Interrupt Acceptance Rev. 6.
Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR * SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling Legend: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register Stack pointer SP: Notes: 1.
Rev. 6.00 Aug 04, 2006 page 112 of 680 REJ09B0145-0600 Internal data bus (16 bits) Internal write signal Internal read signal Internal address bus φ Interrupt request signal Figure 3.5 Interrupt Sequence (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (10) (9) Prefetch instruction of Internal interrupt-handling routine processing (1) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note: * Not including EEPMOV instruction. Rev. 6.
Section 3 Exception Handling 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3847R Group, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
Section 3 Exception Handling 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ4 to IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin.
Section 3 Exception Handling Table 3.5 Conditions Under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 IRR1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Conditions When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0.
Section 3 Exception Handling An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. CCR I bit←1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction After setting the port mode register bit, first execute at least one instruction (e.g.
Section 3 Exception Handling 3.4.3 Method for Clearing Interrupt Request Flags Use the recommended method, given below when clearing the flags of interrupt request registers (IRR1, IRR2, IWPR). • Recommended method Use a single instruction to clear flags. The bit control instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are given below. BCLR #1, @IRR1:8 MOV.
Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4.
Section 4 Clock Pulse Generators 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a Crystal Oscillator Figure 4.2 shows a typical method of connecting a crystal oscillator. For information on recommended resonators, see the product AC characteristics listed in section 15, Electrical Characteristics.
Section 4 Clock Pulse Generators Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.4.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C1 OSC 1 OSC 2 C2 Figure 4.4 Board Design of Oscillator Circuit 4. External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open.
Section 4 Clock Pulse Generators The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board. When using the oscillator, consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 4.3 Subclock Generator 1. Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.6.
Section 4 Clock Pulse Generators 2. Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure 4.8. X1 GND X2 Open Figure 4.8 Pin Connection when not Using Subclock 3. External Clock Input • H8/3847R Group and H8/3847S Group Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.9 (a). X1 X2 External clock input Open Figure 4.
Section 4 Clock Pulse Generators • H8/38347 Group and H8/38447 Group Connect pin X1 to GND and leave pin X2 open. Input an external clock to pin EXCL. Set bit EXCL in register PMR2 to 1 to supply the external clock to the internal components of the device. A connection example is shown in figure 4.9 (b). X1 GND X2 Open P31/UD/EXCL External clock input Figure 4.9 (b) Pin Connection when Inputting External Clock (H8/38347 Group and H8/38447 Group) Frequency Subclock (φ φw) Duty 45% to 55% 4.
Section 4 Clock Pulse Generators 4.4 Prescalers The H8/3847R Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φW/4) as its input clock.
Section 4 Clock Pulse Generators 4.5 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM, ZTAT™ and F-ZTAT™ versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer.
Section 4 Clock Pulse Generators Modification point OSC1 OSC1 C1 C1 Rf Rf OSC2 OSC2 C2 C2 Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 Modification point Modification point C3 OSC1 C1 OSC1 C1 Rf C2 Rf OSC2 OSC2 (3) Oscillator Circuit Modification Suggestion 2 C2 (4) Oscillator Circuit Modification Suggestion 3 Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.
Section 4 Clock Pulse Generators 1. Oscillation Stabilization Time (trc) The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Wait Time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized.
Section 4 Clock Pulse Generators amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required.
Section 4 Clock Pulse Generators If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. Rev. 6.
Section 5 Power-Down Modes Section 5 Power-Down Modes 5.1 Overview This LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes. Table 5.
Section 5 Power-Down Modes Program execution state Reset state SLEEP instruction(a) Active (high-speed) mode P (d) EE SL uction tr ins Program halt state Program halt state ) P (a EE tion L c S ru st inin SL st E ru E ct P io n (b SLEEP instruction(f) SL instr EEP uctio (d n ) (4) ) i (1) SLEEP instruction(e) (1) Subactive mode SLEEP instruction(b) (3) Sleep (medium-speed) mode ins SLE tru EP cti on (j) ins SLE tru EP ctio n (i) ) SLEEP instruction(i) P (e EE tion L S ruc t ns SLEEP i
Section 5 Power-Down Modes Table 5.
Section 5 Power-Down Modes 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name Abbreviation R/W Initial Value Address System control register 1 SYSCR1 R/W H'07 H'FFF0 System control register 2 SYSCR2 R/W H'F0 H'FFF1 1.
Section 5 Power-Down Modes Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation settling time.
Section 5 Power-Down Modes Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose φOSC/128, φOSC/64, φOSC/32, or φOSC/16 as the operating clock in active (medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-speed) mode or subactive mode. Bit 1 MA1 Bit 0 MA0 Description 0 0 φOSC/16 0 1 φOSC/32 1 0 φOSC/64 1 1 φOSC/128 (initial value) 2.
Section 5 Power-Down Modes Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits.
Section 5 Power-Down Modes Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 Bit 0 SA0 Description 0 0 φW /8 0 1 φW /4 1 * φW /2 Note: * (initial value) Don’t care 5.2 Sleep Mode 5.2.1 Transition to Sleep Mode 1.
Section 5 Power-Down Modes 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter, IRQ4 to IRQ0, WKP7 to WKP0, SCI1, SCI3-1, SCI3-2, or A/D converter), or by input at the RES pin. • Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Section 5 Power-Down Modes 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Section 5 Power-Down Modes Table 5.4 Clock Frequency and Settling Time (Times are in ms) STS2 STS1 STS0 Waiting Time 2 MHz 1 MHz 0 0 0 8,192 states 4.1 8.2 0 0 1 16,384 states 8.2 16.4 0 1 0 32,768 states 16.4 32.8 0 1 1 65,536 states 32.8 65.5 1 0 0 131,072 states 65.5 131.1 1 0 1 2 states (not available) 0.001 0.002 1 1 0 8 states 0.004 0.008 1 1 1 16 states 0.008 0.
Section 5 Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ or WKP is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred to together in this section as the internal clock).
Section 5 Power-Down Modes Operating mode Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc Wait for Active (high-speed, Standby mode oscillation medium-speed) mode or watch mode to settle or subactive mode tcyc tsubcyc tcyc tsubcyc φ or φSUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signall Figure 5.
Section 5 Power-Down Modes 5.4 Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, AEC, and the LCD controller/driver (for which operation or halting can be set) is halted.
Section 5 Power-Down Modes 5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D converter, PWM and WDT is halted.
Section 5 Power-Down Modes 5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI1, SCI3-1, SCI3-2, IRQ4 to IRQ0, or WKP7 to WKP0 interrupt is requested.
Section 5 Power-Down Modes 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1, or WKP7 to WKP0 interrupts in standby mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode.
Section 5 Power-Down Modes 5.8 Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts.
Section 5 Power-Down Modes • Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Section 5 Power-Down Modes 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Section 5 Power-Down Modes 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Section 5 Power-Down Modes 5.9 Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode.
Section 5 Power-Down Modes Table 5.
Section 5 Power-Down Modes 5.9.3 Usage Note If, due to the timing with which a peripheral module issues interrupt requests, the module in question is set to module standby mode before an interrupt is processed, the module will stop with the interrupt request still pending. In this situation, interrupt processing will be repeated indefinitely unless interrupts are prohibited. It is therefore necessary to ensure that no interrupts are generated when a module is set to module standby mode.
Section 6 ROM Section 6 ROM 6.1 Overview The H8/3842R, H8/38342, and H8/38442 have 16 Kbytes of mask ROM, the H8/3843R, H8/38343, and H8/38443 have 24 Kbytes of mask ROM, the H8/3844R, H8/3844S, H8/38344, and H8/38444 have 32 Kbytes of mask ROM, the H8/3845R, H8/3845S, H8/38345, and H8/38445 have 40 Kbytes of mask ROM, the H8/3846R, H8/3846S, H8/38346, and H8/38446 have 48 Kbytes of mask ROM, and the H8/3847R, H8/3847S, H8/38347, and H8/38447 have 60 Kbytes of mask ROM on-chip.
Section 6 ROM 6.1.1 Block Diagram Figure 6.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0000 H'0001 H'0002 H'0002 H'0003 On-chip ROM H'7FFE H'7FFE H'7FFF Even-numbered address Odd-numbered address Figure 6.1 ROM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444) Rev. 6.
Section 6 ROM 6.2 PROM Mode (H8/3847R) 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set the chip to PROM mode. Table 6.1 Setting to PROM Mode Pin Name Setting TEST High level PB4/AN4 Low level PB5/AN5 PB6/AN6 6.2.
Section 6 ROM H8/3847R EPROM socket HN27C101 (32-pin) FP-100B, TFP-100B FP-100A Pin Pin 15 18 RES VPP 1 51 54 P60 EO0 13 52 55 P61 EO1 14 53 56 P62 EO2 15 54 57 P63 EO3 17 55 58 P64 EO4 18 56 59 P65 EO5 19 57 60 P66 EO6 20 58 61 P67 EO7 21 74 77 P87 EA0 12 73 76 P86 EA1 11 72 75 P85 EA2 10 71 74 P84 EA3 9 70 73 P83 EA4 8 69 72 P82 EA5 7 68 71 P81 EA6 6 67 70 P80 EA7 5 59 62 P70 EA8 27 86 89 P43 EA9 26 61 6
Section 6 ROM Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'EDFF H'EDFF Uninstalled area* H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be possible to continue PROM programming and verification.
Section 6 ROM 6.3 Programming (H8/3847R) The write, verify, and other modes are selected as shown in table 6.3 in PROM mode. (H8/3847R) Table 6.
Section 6 ROM Start Set write/verify mode VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V Address = 0 n=0 n+1 →n No Yes n < 25 Write time t PW = 0.2 ms ± 5% No Go Address + 1 → address Verify Go Write time tOPW = 0.2n ms Last address? No Yes Set read mode VCC = 5.0 V ± 0.25 V, VPP = VCC No Go Error Read all addresses? Go End Figure 6.4 High-Speed, High-Reliability Programming Flow Chart Rev. 6.
Section 6 ROM Tables 6.4 and 6.5 give the electrical characteristics in programming mode. Table 6.4 DC Characteristics (Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Input highEO7 to EO0, EA16 to level voltage EA0 OE, CE, PGM VIH 2.4 — VCC + 0.3 V Input lowEO7 to EO0, EA16 to level voltage EA0 OE, CE, PGM VIL –0.3 — 0.8 V Output high- EO7 to EO0 level voltage VOH 2.
Section 6 ROM Table 6.5 AC Characteristics (Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C) Item Symbol Min Typ Max Unit Test Condition Address setup time tAS 2 — — µs OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time 2 — — µs Data output disable time tDH 2 tDF* — — 130 µs VPP setup time tVPS 2 — — µs Programming pulse width tPW 0.19 0.20 0.
Section 6 ROM Figure 6.5 shows a PROM write/verify timing diagram. Write Verify Address tAS Data tAH Input data tDS VPP tDH tDF VPP VCC VCC Output data tVPS VCC+1 VCC tVCS CE tCES PGM tPW tOES tOE OE tOPW* Note: * topw is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6.5 PROM Write/Verify Timing Rev. 6.
Section 6 ROM 6.3.2 Programming Precautions • Use the specified programming voltage and timing. • The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. • Setting the PROM programmer to Renesas specifications for the HN27C101 will result in correct VPP of 12.5 V. • Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned.
Section 6 ROM 6.4 Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6.6 shows the recommended screening procedure. Program chip and verify programmed data Bake chip for 24 to 48 hours at 125°C to 150°C with power off Read and check program Install Figure 6.
Section 6 ROM 6.5 Flash Memory Overview 6.5.1 Features The features of the 60 Kbytes or 32 Kbytes of flash memory built into the F-ZTAT versions are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The 60-Kbyte flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block, 16 Kbytes × 1 block, 8 Kbytes × 1 block and 4 Kbytes × 1 block.
Section 6 ROM 6.5.2 Block Diagram Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 Bus interface/controller EBR Operating mode TES pin P24 pin P26 pin FLPWCR FENR Flash memory Legend: FLMCR1: FLMCR2: EBR: FLPWCR: FENR: Flash memory control register 1 Flash memory control register 2 Erase block register Flash memory power control register Flash memory enable register Figure 6.7 Block Diagram of Flash Memory 6.5.3 Block Configuration Figure 6.
Section 6 ROM H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'0380 H'0381 H'0382 H'0400 H'0401 H'0402 H'0480 H'0481 H'0482 H'0780 H'0781 H'0782 H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 Programming unit: 128 bytes H'007F H'00FF Erase unit 1 Kbyte H'03FF Programming unit: 128 bytes H'047F H'04FF Erase unit 1 Kbyte H'07FF Programming unit: 128 bytes H'087F H'080F Erase unit 1 Kbyte H'0B80 H'0B81 H'0B82 H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000
Section 6 ROM 6.5.4 Register Configuration Table 6.6 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.
Section 6 ROM 6.6 Descriptions of Registers of the Flash Memory 6.6.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 — SWE ESU PSU EV PV E P Initial value 0 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash Memory Programming/Erasing.
Section 6 ROM Bit 5—Erase Setup (ESU) This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time). Bit 5 ESU Description 0 The erase setup state is cancelled 1 The flash memory changes to the erase setup state. Set this bit to 1 before setting the E bit to 1 in FLMCR1. (initial value) Bit 4—Program Setup (PSU) This bit is to prepare for changing to program mode.
Section 6 ROM Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV, E, and P bits at the same time). Bit 2 PV Description 0 Program-verify mode is cancelled 1 The flash memory changes to program-verify mode (initial value) Bit 1—Erase (E) This bit is to set changing to or cancelling erase mode (do not set SWE, ESU, PSU, EV, PV, and P bits at the same time).
Section 6 ROM 6.6.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — — — FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Section 6 ROM Table 6.7 Division of Blocks to Be Erased EBR Bit Name Block (Size) Address 0 EB0 EB0 (1 Kbyte) H'0000 to H'03FF 1 EB1 EB1 (1 Kbyte) H'0400 to H'07FF 2 EB2 EB2 (1 Kbyte) H'0800 to H'0BFF 3 EB3 EB3 (1 Kbyte) H'0C00 to H'0FFF 4 EB4 EB4 (28 Kbytes) H'1000 to H'7FFF 5 EB5 EB5 (16 Kbyte) H'8000 to H'BFFF 6 EB6 EB6 (8 Kbyte) H'C000 to H'DFFF 7 EB7 EB7 (4 Kbytes) H'E000 to H'EFFF 6.6.
Section 6 ROM 6.6.5 Flash Memory Enable Register (FENR) Bit 7 6 5 4 3 2 1 0 FLSHE — — — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write R/W — — — — — — — FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and FLPWCR. Bit 7—Flash Memory Control Register Enable (FLSHE) This bit controls access to the flash memory control registers.
Section 6 ROM 6.7 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, the device changes to a mode depending on the TEST pin settings, P24 pin settings, and input level of each port, as shown in table 6.8.
Section 6 ROM 6.7.1 Boot Mode Table 6.9 shows the boot mode operations between reset end and branching to the programming control program. The device uses SCI32 in the boot mode. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing. 2.
Section 6 ROM 8. Do not change the TEST pin and P24 pin input levels in boot mode. Table 6.9 Boot Mode Operation Host Operation LSI Operation Item Processing Contents Processing Contents Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Flash memory erase Transmits data H'55 when data H'00 is received and no error occurs. Branches to boot program at reset-start. · Measures low-level period of receive data H'00. · Calculates bit rate and sets it in BRR of SCI3.
Section 6 ROM 6.7.2 Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Section 6 ROM program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2, Erase/Erase-Verify, respectively. 6.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed.
Section 6 ROM Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait 50 µs n=1 Set P bit in FLMCR1 m=0 Wait (Wait time = programming time) Write 128-byte data in RAM reprogram data area consecutively to flash memory Clear P bit in FLMCR1 Apply Write pulse Wait 5 µs Set PV bit in FLMCR1 Clear PSU bit in FLMCR1 Wait 4 µs Wait 5 µs Set block start addre
Section 6 ROM Table 6.11 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 6.
Section 6 ROM 6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 6 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 Wait 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs n←n+1 Read verify data No Verify data = all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes No Yes SWE bit ← 0 SWE bit ← 0
Section 6 ROM 6.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode.
Section 6 ROM by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 6.10 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory (F-ZTAT64V3).
Section 6 ROM Table 6.14 Command Sequence in Programmer Mode 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read 1+n Write X H'00 Read RA Dout Auto-program 129 Write X H'40 Write WA Din Auto-erase 2 Write X H'20 Write X H'20 Status read 2 Write X H'71 Write X H'71 n: the number of address write cycles Rev. 6.
Section 6 ROM F-ZTAT Device Pin No. FP-100B TFP-100B TFP-100G Pin Name 60 P71 66 3 51 52 53 54 55 56 57 58 74 73 72 71 70 69 68 67 59 85 61 62 63 64 65 86 32, 38 87 9 14 36 5 P77 P12 P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 P42 P72 P73 P74 P75 P76 P43 CVcc, Vcc AVcc X1 TEST V1 P14 100, 11 33 88 89 90 13, 12 15 Other than the above AVss, Vss Vss PB0 PB1 PB2 OSC1, OSC2 RES (OPEN) Socket Adapter (Conversion to 32-Pin Arrangement) HN28F101 (32 Pins) Pin Name Pin No.
Section 6 ROM 6.10.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3.
Section 6 ROM Command write Memory read mode Address stable A15−A0 tces tceh tnxtc CE OE twep tf tr WE tds tdh I/O7−I/O0 Note: Data is latched on the rising edge of WE. Figure 6.13 Timing Waveforms for Memory Read after Memory Write Table 6.16 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 — µs Figure 6.
Section 6 ROM Memory read mode A15−A0 Other mode command write Address stable tces tnxtc tceh CE OE twep tf tr WE tds tdh I/O7−I/O0 Note: Do not enable WE and OE at the same time. Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode Table 6.17 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Access time tacc — 20 µs Figure 6.15 CE output delay time tce — 150 ns Figure 6.
Section 6 ROM A15−A0 Address stable Address stable tce tce CE toe toe OE WE tacc tacc toh tdf toh tdf I/O7−I/O0 Figure 6.16 CE and OE Clock System Read Timing Waveforms 6.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3.
Section 6 ROM Table 6.18 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 — µs Figure 6.
Section 6 ROM 6.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write.
Section 6 ROM A15−A0 tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds terase tdh I/O7 Erase end decision signal I/O6 Erase normal end decision signal I/O5−I/O0 H'20 H'20 H'00 Figure 6.18 Auto-Erase Mode Timing Waveforms 6.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2.
Section 6 ROM Table 6.20 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Read time after command write tnxtc 20 — µs Figure 6.
Section 6 ROM Table 6.21 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 0 1: Abnormal end 0: Normal end I/O6 0 I/O5 0 1: Command error 0: Otherwise 1: Programming error 0: Otherwise I/O4 0 1: Erasing error 0: Otherwise I/O3 0 I/O2 0 I/O1 0 1: Over counting of writing or erasing 0: Otherwise I/O0 0 1: Effective address error 0: Otherwise 6.10.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
Section 6 ROM 6.10.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 6.23 Stipulated Transition Times to Command Wait State Item Symbol Min Max Unit Notes Oscillation stabilization time(crystal oscillator) Tosc1 10 — ms Figure 6.
Section 6 ROM 6.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down operating mode The power supply circuit of the flash memory is partly halted and can be read under low power consumption. • Standby mode All flash memory circuits are halted. Table 6.24 shows the correspondence between the operating modes of this LSI and the flash memory.
Section 7 RAM Section 7 RAM 7.1 Overview The H8/3842R, H8/3843R, H8/38342, H8/38343, H8/38442, and H8/38443 have 1 Kbytes of high-speed static RAM, and H8/3844R, H8/3844S, H8/38344, H8/38444, H8/3845R, H8/3845S, H8/38345, H8/38445, H8/3846R, H8/3846S, H8/38346, H8/38446, H8/3847R, H8/3847S, H8/38347, and H8/38447 have 2 Kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.
Section 7 RAM Rev. 6.
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The H8/3847R Group, H8/3847S Group and H8/38347 Group are provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits.
Section 8 I/O Ports Port Description Port 3 • 8-bit I/O port • MOS input pull-up option Function Switching Registers Pins Other Functions P37/AEVL P36/AEVH P35/TXD31 P34/RXD31 P33/SCK31 SCI3-1 data output (TXD31), data PMR3 input (RXD31), clock input/output SCR31 (SCK31), and asynchronous counter SMR31 event inputs AEVL, AEVH • Large-current port (H8/3847R Group, 1 P32/RESO* H8/38347 Group 2 P31/UD/EXCL* and H8/38447 P30/PWM Group) Reset output* , timer C count-up/ down select input, and 14-bit PW
Section 8 I/O Ports 8.2 Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration. P1 7 /IRQ 3 /TMIF P1 6 /IRQ 2 P1 5 /IRQ 1 /TMIC Port 1 P1 4 /IRQ 4 /ADTRG P1 3 /TMIG P1 2 /TMOFH P1 1 /TMOFL P1 0 /TMOW Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbr.
Section 8 I/O Ports 1. Port Data Register 1 (PDR1) Bit 7 6 5 4 3 2 1 0 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR1 is an 8-bit register that stores data for port 1 pins P17 to P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 4. Port Mode Register 1 (PMR1) Bit 7 6 5 4 3 2 1 0 IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7: P17/IRQ3/TMIF pin function switch (IRQ3) This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF.
Section 8 I/O Ports Bit 5: P15/IRQ1/TMIC pin function switch (IRQ1) This bit selects whether pin P15/IRQ1/TMIC is used as P15 or as IRQ1/TMIC. Bit 5 IRQ1 Description 0 Functions as P15 I/O pin 1 Functions as IRQ1/TMIC input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1/TMIC. For details of TMIC pin setting, see 1. Timer mode register C (TMC) in section 9.3.2.
Section 8 I/O Ports Bit 1: P11/TMOFL pin function switch (TMOFL) This bit selects whether pin P11/TMOFL is used as P11 or as TMOFL. Bit 1 TMOFL Description 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin (initial value) Bit 0: P10/TMOW pin function switch (TMOW) This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0 TMOW Description 0 Functions as P10 I/O pin 1 Functions as TMOW output pin (initial value) Rev. 6.
Section 8 I/O Ports 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P17/IRQ3/TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function 0 0 1 1 * 0** IRQ3/TMIF input pin Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1 to disable the IRQ3 interrupt.
Section 8 I/O Ports Pin Pin Functions and Selection Method P13/TMIG The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1. TMIG PCR13 Pin function P12/TMOFH 0 0 P13 input pin 1 P13 output pin 1 * TMIG input pin The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function P11/TMOFL 0 0 P12 input pin 1 P12 output pin 1 * TMOFH output pin The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1.
Section 8 I/O Ports 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n 0 0 1 PUCR1n 0 1 * MOS input pull-up Off On Off (n = 7 to 0) *: Don’t care Rev. 6.
Section 8 I/O Ports 8.3 Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Figure 8.2 shows its pin configuration. In the F-ZTAT version, the on-chip pull-up MOS for pin P24 is on during the reset period. It turns off and normal operation resumes after the reset is cleared. The pull-up MOS is controlled by hardware; it cannot be manipulated by a user program. This should be considered when making connections to external circuitry. Note that the mask ROM and ZTAT versions do not have this function.
Section 8 I/O Ports 1. Port Data Register 2 (PDR2) Bit 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR2 is an 8-bit register that stores data for port 2 pins P27 to P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports • H8/38347 Group and H8/38447 Group Bit 7 6 5 4 3 2 1 0 EXCL — POF1 — — SO1 SI1 SCK1 Initial value 0 1 0 1 1 0 0 0 Read/Write R/W — R/W — — R/W R/W R/W PMR2 is an 8-bit read/write register that controls the selection of pin functions for pins P20, P21, and P23, the PMOS on/off state for the P22/SO1 pin, and external clock input to pin P31. Upon reset, PMR2 is initialized to H'58.
Section 8 I/O Ports Bit 2: P22/SO1 pin function switch (SO1) This bit selects whether pin P22/SO1 is used as P22 or as SO1. Bit 2 SO1 Description 0 Functions as P22 I/O pin 1 Functions as SO1 output pin (initial value) Bit 1: P21/SI1 pin function switch (SI1) This bit selects whether pin P21/SI1 is used as P21 or as SI1.
Section 8 I/O Ports Bit n: NMOS open-drain output select (NMODn) These bits select NMOS open-drain output when pin P2n is used as an output pin. Bit n NMODn Description 0 CMOS output 1 NMOS open-drain output (initial value) (n = 7 to 0) 8.3.3 Pin Function Table 8.6 shows the port 2 pin functions. Table 8.6 Port 2 Pin Functions Pin Pin Functions and Selection Method P27 to P23 The pin function depends on the corresponding bit in PCR2.
Section 8 I/O Ports 8.3.4 Pin States Table 8.7 shows the port 2 pin states in each operating mode. Table 8.7 Port 2 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P27 to P25 Highimpedance Retains previous state Functional Functional Pull-up MOS on Retains previous state Highimpedance P24*1 Retains previous state P24*2 P23 Highimpedance P22/SO1 P21/SI1 P20/SCK1 Highimpedance Notes: 1. Applies to the F-ZTAT version of the H8/38347 Group and H8/38447 Group. 2.
Section 8 I/O Ports 8.4 Port 3 8.4.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.3. P3 7 /AEVL P3 6 /AEVH P3 5 /TXD31 P3 4 /RXD31 Port 3 P3 3 /SCK 31 P3 2 /RESO*1 P3 1 /UD/EXCL*2 P3 0 /PWM Notes: 1. The RESO function is not implemented in the H8/38347 Group and H8/38447 Group. 2. The EXCL function only applies to the H8/38347 Group and H8/38447 Group. Figure 8.3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8.
Section 8 I/O Ports 1. Port Data Register 3 (PDR3) Bit 7 6 5 4 3 2 1 0 P3 7 P36 P35 P34 P3 3 P32 P31 P3 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 4. Port Mode Register 3 (PMR3) Bit 7 6 5 4 3 2 1 0 AEVL AEVH WDCKS NCS IRQ0 RESO* UD PWM Initial value 0 0 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'04. Note: * The RESO bit is not implemented in the H8/38347 Group and H8/38447 Group.
Section 8 I/O Ports Bit 4: TMIG noise canceler select (NCS) This bit controls the noise canceler for the input capture input signal (TMIG). Bit 4 NCS Description 0 Noise cancellation function not used 1 Noise cancellation function used (initial value) Bit 3: P43/IRQ0 pin function switch (IRQ0) This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Section 8 I/O Ports In the H8/38347 Group and H8/38447 Group this pin is a combined P31/UD/EXCL pin. Refer to the description of port mode register 2 in 8.3, Port 2, for details on switching to the EXCL pin function. Bit 0: P30/PWM pin function switch (PWM) This bit selects whether pin P30/PWM is used as P30 or as PWM. Bit 0 PWM Description 0 Functions as P30 I/O pin 1 Functions as PWM output pin 8.4.3 (initial value) Pin Functions Table 8.9 shows the port 3 pin functions. Table 8.
Section 8 I/O Ports Pin Pin Functions and Selection Method P33/SCK31 The pin function depends on bits CKE1, CKE0, and SMR31 in SCR3-1 and bit PCR33 in PCR3.
Section 8 I/O Ports 8.4.4 Pin States Table 8.10 shows the port 3 pin states in each operating mode. Table 8.10 Port 3 Pin States Pins Reset Sleep Subsleep Standby P37/AEVL P36/AEVH P35/TXD31 P34/RXD31 P33/SCK31 Highimpedance Retains previous state Retains previous state HighRetains impedance*1 previous state P32/RESO*2 Reset output P32*3 P31/UD*2 P31/UD/EXCL*3 P30/PWM Highimpedance Watch Subactive Active Functional Functional Notes: 1.
Section 8 I/O Ports 8.5 Port 4 8.5.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.4. P4 3 /IRQ0 P4 2 /TXD32 Port 4 P4 1 /RXD32 P4 0 /SCK32 Figure 8.4 Port 4 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 4 register configuration. Table 8.11 Port 4 Registers Name Abbr. R/W Initial Value Address Port data register 4 PDR4 R/W H'F8 H'FFD7 Port control register 4 PCR4 W H'F8 H'FFE7 1.
Section 8 I/O Ports 2. Port Control Register 4 (PCR4) Bit 7 6 5 4 3 2 1 0 — — — — — PCR42 PCR4 1 PCR4 0 Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 8 I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 4 pin functions. Table 8.12 Port 4 Pin Functions Pin Pin Functions and Selection Method P43/IRQ0 The pin function depends on bit IRQ0 in PMR3. IRQ0 Pin function P42/TXD32 0 0 1 1 * TXD32 output pin 1 P42 output pin 0 P42 input pin The pin function depends on bit RE in SCR3-2 and bit PCR41 in PCR4.
Section 8 I/O Ports 8.5.4 Pin States Table 8.13 shows the port 4 pin states in each operating mode. Table 8.13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43/IRQ0 P42/TXD32 P41/RXD32 P40/SCK32 Highimpedance Retains previous state Retains previous state Highimpedance Retains previous state Functional Functional Rev. 6.
Section 8 I/O Ports 8.6 Port 5 8.6.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.5. P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 Port 5 P54/WKP4/SEG5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 Figure 8.5 Port 5 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 5 register configuration. Table 8.14 Port 5 Registers Name Abbr.
Section 8 I/O Ports 1. Port Data Register 5 (PDR5) Bit 7 6 5 4 3 2 1 0 P5 7 P5 6 P55 P5 4 P53 P52 P51 P5 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports Upon reset, PUCR5 is initialized to H'00. 4. Port Mode Register 5 (PMR5) Bit 7 6 5 4 3 2 1 0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00.
Section 8 I/O Ports 8.6.4 Pin States Table 8.16 shows the port 5 pin states in each operating mode. Table 8.16 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P57/WKP7/ SEG8 to P50/ WKP0/SEG1 Highimpedance Retains previous state Retains previous state Highimpedance* Retains previous state Functional Functional Note: * 8.6.5 A high-level signal is output when the MOS pull-up is in the on state.
Section 8 I/O Ports 8.7 Port 6 8.7.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.6. P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 Port 6 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 Figure 8.6 Port 6 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 6 register configuration. Table 8.17 Port 6 Registers Name Abbr.
Section 8 I/O Ports 1. Port Data Register 6 (PDR6) Bit 7 6 5 4 3 2 1 0 P6 7 P66 P65 P64 P6 3 P62 P61 P6 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 3. Port Pull-Up Control Register 6 (PUCR6) Bit 7 6 5 4 3 2 1 0 PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off.
Section 8 I/O Ports 8.7.5 MOS Input Pull-Up Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR6n 0 0 1 PUCR6n 0 1 * MOS input pull-up Off On Off (n = 7 to 0) *: Don’t care Rev. 6.
Section 8 I/O Ports 8.8 Port 7 8.8.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.7. P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 Port 7 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 Figure 8.7 Port 7 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 7 register configuration. Table 8.20 Port 7 Registers Name Abbr. R/W Initial Value Address Port data register 7 PDR7 R/W H'00 H'FFDA Port control register 7 PCR7 W H'00 H'FFEA Rev.
Section 8 I/O Ports 1. Port Data Register 7 (PDR7) Bit 7 6 5 4 3 2 1 0 P7 7 P7 6 P75 P7 4 P73 P72 P71 P70 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 8.8.3 Pin Functions Table 8.21 shows the port 7 pin functions. Table 8.21 Port 7 Pin Functions Pin Pin Functions and Selection Method P77/SEG24 to P70/SEG17 The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in LPCR. (n = 7 to 0) SGS3 to SGS0 PCR7n Pin function 00** 0 P7n input pin 1 P7n output pin 01**, 1*** * SEGn+17 output pin *: Don’t care 8.8.4 Pin States Table 8.22 shows the port 7 pin states in each operating mode. Table 8.
Section 8 I/O Ports 8.9 Port 8 8.9.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.8. P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 Port 8 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 Figure 8.8 Port 8 Pin Configuration 8.9.2 Register Configuration and Description Table 8.23 shows the port 8 register configuration. Table 8.23 Port 8 Registers Name Abbr. R/W Initial Value Address Port data register 8 PDR8 R/W H'00 H'FFDB Port control register 8 PCR8 W H'00 H'FFEB Rev. 6.
Section 8 I/O Ports 1. Port Data Register 8 (PDR8) Bit 7 6 5 4 3 2 1 0 P8 7 P8 6 P85 P8 4 P83 P82 P81 P8 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 8.9.3 Pin Functions Table 8.24 shows the port 8 pin functions. Table 8.24 Port 8 Pin Functions Pin Pin Functions and Selection Method P87/SEG32 to P80/SEG25 The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in LPCR. (n = 7 to 0) SGS3 to SGS0 PCR8n Pin function 000* 1 P8n output pin 0 P8n input pin 001*, 01**,1*** * SEGn+25 output pin *: Don’t care 8.9.4 Pin States Table 8.25 shows the port 8 pin states in each operating mode. Table 8.
Section 8 I/O Ports 8.10 Port 9 8.10.1 Overview Port 9 is an 8-bit I/O port. Figure 8.9 shows its pin configuration. P97/SEG40/CL1* P96/SEG39/CL2* P95/SEG38/DO* P94/SEG37/M* Port 9 P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 Note: * The CL1, CL2, DO, and M functions are not implemented on the H8/38347 Group and H8/38447 Group. Figure 8.9 Port 9 Pin Configuration 8.10.2 Register Configuration and Description Table 8.26 shows the port 9 register configuration. Table 8.26 Port 9 Registers Name Abbr.
Section 8 I/O Ports 1. Port Data Register 9 (PDR9) Bit 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 8.10.3 Pin Functions Table 8.27 shows the port 9 pin functions. The SGX = 0 setting also functions on the H8/38347 and H8/38447. Table 8.27 Port 9 Pin Functions Pin Pin Functions and Selection Method P97/SEG40/CL1 The pin function depends on bit PCR97 in PCR9 and bits SGX and SGS3 to SGS0 in LPCR.
Section 8 I/O Ports Pin Pin Functions and Selection Method P93/SEG36 to P90/SEG33 The pin function depends on bit PCR9n in PCR9 and bits SGS3 to SGS0 in LPCR. (n = 3 to 0) SGS3 to SGS0 PCR9n Pin function 0000 0 1 P9n input pin P9n output pin Not 0000 * SEGn+33 output pin *: Don’t care 8.10.4 Pin States Table 8.28 shows the port 9 pin states in each operating mode. Table 8.
Section 8 I/O Ports 8.11 Port A 8.11.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8.10. PA3/COM4 PA2/COM3 Port A PA1/COM2 PA0/COM1 Figure 8.10 Port A Pin Configuration 8.11.2 Register Configuration and Description Table 8.29 shows the port A register configuration. Table 8.29 Port A Registers Name Abbr. R/W Initial Value Address Port data register A PDRA R/W H'F0 H'FFDD Port control register A PCRA W H'F0 H'FFED 1.
Section 8 I/O Ports 2. Port Control Register A (PCRA) Bit 7 6 5 4 — — — — Initial value 1 1 1 1 Read/Write — — — — 3 0 2 1 PCRA 2 PCRA 1 0 0 0 0 R/W R/W R/W R/W PCRA 3 PCRA 0 PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 8 I/O Ports 8.11.3 Pin Functions Table 8.30 shows the port A pin functions. Table 8.30 Port A Pin Functions Pin Pin Functions and Selection Method PA3/COM4 The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 PCRA3 Pin function PA2/COM3 0000 0 1 PA2 input pin PA2 output pin Not 0000 * COM3 output pin The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
Section 8 I/O Ports 8.12 Port B 8.12.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8.11. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 8.11 Port B Pin Configuration 8.12.2 Register Configuration and Description Table 8.32 shows the port B register configuration. Table 8.32 Port B Register Name Abbr. R/W Address Port data register B PDRB R H'FFDE 1.
Section 8 I/O Ports 8.13 Port C 8.13.1 Overview Port C is a 4-bit input-only port, configured as shown in figure 8.12. PC3/AN11 PC2/AN10 Port C PC1/AN9 PC0/AN8 Figure 8.12 Port C Pin Configuration 8.13.2 Register Configuration and Description Table 8.33 shows the port C register configuration. Table 8.33 Port C Register Name Abbr. R/W Address Port data register C PDRC R H'FFDF 1.
Section 8 I/O Ports Reading the pin for which an analog input channel is selected by the AMR CH3 to CH0 of the A/D converter, "0" is read regardless of the input voltage. 8.14 Input/Output Data Inversion Function 8.14.1 Overview With input pins RXD31, and RXD32, and output pins TXD31 and TXD32, the data can be handled in inverted form. SCINV0 SCINV2 RXD31 RXD32 P34/RXD31 P41/RXD32 SCINV1 SCINV3 P35/TXD31 P42/TXD32 TXD31 TXD32 Figure 8.13 Input/Output Data Inversion Function 8.14.
Section 8 I/O Ports 1. Serial Port Control Register (SPCR) Bit 7 6 5 4 — — SPC32 SPC31 Initial value 1 1 0 0 0 0 0 0 Read/Write — — R/W R/W R/W R/W R/W R/W 3 2 1 0 SCINV3 SCINV2 SCINV1 SCINV0 SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin input/output data inversion switching. SPCR is initialized to H'C0 by a reset. Bits 7 and 6: Reserved bits Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Section 8 I/O Ports Bit 3: TXD32 pin output data inversion switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3 Description 0 TXD32 output data is not inverted 1 TXD32 output data is inverted (initial value) Bit 2: RXD32 pin input data inversion switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Section 8 I/O Ports 8.14.3 Note on Modification of Serial Port Control Register When a serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying a serial port control register, do so in a state in which data changes are invalidated. 8.15 Application Note 8.15.
Section 9 Timers Section 9 Timers 9.1 Overview This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.
Section 9 Timers Name Functions Asynchro- • 16-bit counter nous event • Also usable as two counter independent 8-bit counters Internal Clock — Event Waveform Input Pin Output Pin Remarks AEVL AEVH — • Counts events asynchronous to φ and φW 9.2 Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768 kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz, from 38.
Section 9 Timers 2. Block Diagram Figure 9.1 shows a block diagram of timer A.
Section 9 Timers 4. Register Configuration Table 9.3 shows the register configuration of timer A. Table 9.3 Timer A Registers Name Abbr. R/W Initial Value Address Timer mode register A TMA R/W H'10 H'FFB0 Timer counter A TCA R H'00 H'FFB1 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA Subclock output select register CWOSR R/W H'FE H'FF92 9.2.2 Register Descriptions 1.
Section 9 Timers Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. φw is output in all modes except the reset state.
Section 9 Timers Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period 0 0 0 0 PSS, φ/8192 1 PSS, φ/4096 1 0 PSS, φ/2048 1 PSS, φ/512 0 0 PSS, φ/256 1 PSS, φ/128 0 PSS, φ/32 1 PSS, φ/8 0 PSW, 1 s Clock time base 1 PSW, 0.5 s (when using 0 PSW, 0.25 s 32.768 kHz) 1 PSW, 0.
Section 9 Timers 2. Timer Counter A (TCA) Bit 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode.
Section 9 Timers 4. Subclock Output Select Register (CWOSR) 7 6 5 4 3 2 1 0 — — — — — — — CWOS Initial value: 1 1 1 1 1 1 1 0 Read/Write: R R R R R R R R/W Bit: CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified.
Section 9 Timers Note: * For details on interrupts, see section 3.3, Interrupts. 2. Real-time Clock Time Base Operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. 3.
Section 9 Timers 9.3 Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer C are given below. • Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an external clock (can be used to count external events). • An interrupt is requested when the counter overflows. • Up/down-counter switching is possible by hardware or software.
Section 9 Timers 2. Block Diagram Figure 9.2 shows a block diagram of timer C. UD φ TCC PSS Internal data bus TMC TMIC TLC φW/4 IRRTC Legend: TMC : TCC : : TLC IRRTC : PSS : Timer mode register C Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S Figure 9.2 Block Diagram of Timer C 3. Pin Configuration Table 9.5 shows the timer C pin configuration. Table 9.5 Pin Configuration Name Abbr.
Section 9 Timers 4. Register Configuration Table 9.6 shows the register configuration of timer C. Table 9.6 Timer C Registers Name Abbr. R/W Initial Value Address Timer mode register C TMC R/W H'18 H'FFB4 Timer counter C TCC R H'00 H'FFB5 Timer load register C TLC W H'00 H'FFB5 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA 9.3.2 Register Descriptions 1.
Section 9 Timers Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter.
Section 9 Timers 2. Timer Counter C (TCC) Bit 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.
Section 9 Timers 4. Clock Stop Register 1 (CKSTPR1) 7 Bit: 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value: 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules.
Section 9 Timers During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 3.3, Interrupts. 2. Auto-reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count.
Section 9 Timers 9.3.4 Timer C Operation States Table 9.7 summarizes the timer C operation states. Table 9.
Section 9 Timers 9.3.5 Usage Note Note the following regarding the operation of timer C. (1) Counting errors caused by external event input Timer counter errors may occur under the following conditions. Conditions • An external event (TMIC) is used in subsleep mode. Symptom • The counter increments or decrements twice for a single external event input.
Section 9 Timers 9.4 Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL). 1. Features Features of timer F are given below.
Section 9 Timers 2. Block Diagram Figure 9.3 shows a block diagram of timer F.
Section 9 Timers 3. Pin Configuration Table 9.8 shows the timer F pin configuration. Table 9.8 Pin Configuration Name Abbr. I/O Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output Timer FL toggle output pin 4. Register Configuration Table 9.9 shows the register configuration of timer F. Table 9.9 Timer F Registers Name Abbr.
Section 9 Timers 9.4.2 Register Descriptions 1. 16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) TCF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Section 9 Timers 2. 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) OCRF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL.
Section 9 Timers 3. Timer Control Register F (TCRF) Bit: 7 6 5 4 3 2 1 0 TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: W W W W W W W W TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins. TCRF is initialized to H'00 upon reset.
Section 9 Timers Bit 3: Toggle output level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description 0 Low level 1 High level (initial value) Bits 2 to 0: Clock select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Section 9 Timers 4. Timer Control/Status Register F (TCSRF) Bit: 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/(W)* R/(W)* R/W R/W R/(W)* R/(W)* R/W R/W Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Section 9 Timers Bit 5: Timer overflow interrupt enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description 0 TCFH overflow interrupt request is disabled 1 TCFH overflow interrupt request is enabled (initial value) Bit 4: Counter clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Section 9 Timers Bit 2: Compare match flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software.
Section 9 Timers Bit 2: Timer F module standby mode control (TFCKSTP) Bit 2 controls setting and clearing of module standby mode for timer F. TFCKSTP Description 0 Timer F is set to module standby mode 1 Timer F module standby mode is cleared 9.4.3 (initial value) CPU Interface TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP).
Section 9 Timers 1. Write Access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9.4 shows an example in which H'AA55 is written to TCF.
Section 9 Timers 2. Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU. Figure 9.
Section 9 Timers 9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers. 1. Timer F Operation Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode.
Section 9 Timers 2. TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b. External event operation External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either the rising or falling edge of external event input.
Section 9 Timers 4. TCF Clear Timing TCF can be cleared by a compare match with OCRF. 5. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. 6. Compare Match Flag set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value).
Section 9 Timers 9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 1. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Section 9 Timers b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point.
Section 9 Timers Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4. Operate interrupt permission (set IENFH, IENFL to 1). Method 2 1.
Section 9 Timers 4. Timer Counter (TCF) Read/Write When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF read value error of ±1. When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal clock except for φw/4 before read/write.
Section 9 Timers • Use of module standby mode enables this module to be placed in standby mode independently when not used. 2. Block Diagram Figure 9.8 shows a block diagram of timer G.
Section 9 Timers 3. Pin Configuration Table 9.11 shows the timer G pin configuration. Table 9.11 Pin Configuration Name Abbr. I/O Function Input capture input TMIG Input Input capture input pin 4. Register Configuration Table 9.12 shows the register configuration of timer G. Table 9.12 Timer G Registers Name Abbr.
Section 9 Timers When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3, Interrupts. TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: * An input capture signal may be generated when TMIG is modified. 2.
Section 9 Timers ICRGR is initialized to H'00 upon reset. 4. Timer Mode Register G (TMG) Bit: Initial value: Read/Write: Note: * 7 6 5 4 3 2 1 0 OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 0 R/(W)* 0 R/(W)* 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Bits 7 and 6 can only be written with 0, for flag clearing.
Section 9 Timers Bit 6: Timer overflow flag L (OVFL) Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It cannot be set by software.
Section 9 Timers Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal.
Section 9 Timers Bit 3: Timer G module standby mode control (TGCKSTP) Bit 3 controls setting and clearing of module standby mode for timer G. TGCKSTP Description 0 Timer G is set to module standby mode 1 Timer G module standby mode is cleared 9.5.3 (initial value) Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in PMR3. Figure 9.
Section 9 Timers Therefore, after making a setting for use of the noise cancellation function, a pulse with at least five times the width of the sampling clock is a dependable input capture signal. Even if noise cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φSUB is necessary to ensure that input capture operations are performed properly Note: * An input capture signal may be generated when the NCS bit is modified. Figure 9.
Section 9 Timers In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Following a reset, TCG starts incrementing on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. When a rising edge/falling edge is detected in the input capture signal input from the TMIG pin, the TCG value at that time is transferred to ICRGR/ICRGF.
Section 9 Timers 3. Input Capture Input Timing a. Without noise cancellation function For input capture input, dedicated input capture functions are provided for rising and falling edges. Figure 9.11 shows the timing for rising/falling edge input capture input. Input capture input signal Input capture signal F Input capture signal R Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function) b.
Section 9 Timers 4. Timing of Input Capture by Input Capture Input Figure 9.13 shows the timing of input capture by input capture input Input capture signal TCG N-1 N N+1 Input capture H'XX register N Figure 9.13 Timing of Input Capture by Input Capture Input 5. TCG Clear Timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9.14 shows the timing for clearing by both edges.
Section 9 Timers 6. Timer G Operation Modes Timer G operation modes are shown in table 9.13. Table 9.
Section 9 Timers Table 9.14 Internal Clock Switching and TCG Operation No.
Section 9 Timers No. Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation 4 Goes from high level to high level Clock before switching Clock before switching Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented. 2.
Section 9 Timers Table 9.
Section 9 Timers When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Section 9 Timers 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG. Figure 9.16 shows an example of the operation in this case. Input capture input signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 9.16 Timer G Application Example Rev. 6.
Section 9 Timers 9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. Features Features of the watchdog timer are given below. • Incremented by internal clock source (φ/8192 or φw/32). • A reset signal is generated when the counter overflows.
Section 9 Timers 3. Register Configuration Table 9.17 shows the register configuration of the watchdog timer. Table 9.17 Watchdog Timer Registers Name Abbr. R/W Initial Value Address Timer control/status register W TCSRW R/W H'AA H'FFB2 Timer counter W TCW R/W H'00 H'FFB3 Clock stop register 2 CKSTP2 R/W H'FF H'FFFB Port mode register 3 PMR3 R/W H'00 H'FFCA 9.6.2 Register Descriptions 1.
Section 9 Timers Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE Description 0 Data cannot be written to TCW 1 Data can be written to TCW (initial value) Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI Description 0 Bit 4 is write-enabled 1 Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored.
Section 9 Timers Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON Description 0 Watchdog timer operation is disabled Clearing condition: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON 1 Watchdog timer operation is enabled Setting condition: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON (initial value) Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Section 9 Timers 2. Timer Counter W (TCW) Bit 7 6 5 4 3 2 1 0 TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is φ/8192 or φw/32. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW.
Section 9 Timers 4. Port Mode Register 3 (PMR3) Bit 7 6 5 4 — — — — 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — R/W R/W R/W R/W AECKSTP WDCKSTP PWCKSTP LDCKSTP PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3 pins. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports.
Section 9 Timers Figure 9.18 shows an example of watchdog timer operations. Example: φ = 2 MHz and the desired overflow period is 30 ms. 2 × 106 × 30 × 10–3 = 7.3 8192 The value set in TCW should therefore be 256 – 8 = 248 (H'F8). TCW overflow H'FF H'F8 TCW count value H'00 Start H'F8 written in TCW H'F8 written in TCW Reset Internal reset signal 512 φOSC clock cycles Figure 9.18 Typical Watchdog Timer Operations (Example) Rev. 6.
Section 9 Timers 9.6.4 Watchdog Timer Operation States Table 9.18 summarizes the watchdog timer operation states. Table 9.18 Watchdog Timer Operation States Operation Mode Reset Active TCW Reset Functions Functions Halted Functions/ Halted Halted* Halted Halted TCSRW Reset Functions Functions Retained Functions/ Retained Halted* Retained Retained Note: * Sleep Watch Subactive Subsleep Standby Module Standby Functions when φw/32 is selected as the input clock. Rev. 6.
Section 9 Timers 9.7 Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock input. 1. Features Features of the asynchronous event counter are given below. • Can count asynchronous events • Can count external events input asynchronously without regard to the operation of base clocks φ and φSUB. • The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
Section 9 Timers 2. Block Diagram Figure 9.19 shows a block diagram of the asynchronous event counter. IRREC OVH ECH CK ECL CK AEVH Internal data bus ECCSR OVL AEVL Legend: ECCSR ECH ECL AEVH AEVL IRREC : Event counter control/status register : Event counter H : Event counter L : Asynchronous event input H : Asynchronous event input L : Event counter overflow interrupt request flag Figure 9.19 Block Diagram of Asynchronous Event Counter 3. Pin Configuration Table 9.
Section 9 Timers 4. Register Configuration Table 9.20 shows the register configuration of the asynchronous event counter. Table 9.20 Asynchronous Event Counter Registers Name Abbr. R/W Initial Value Address Event counter control/status register ECCSR R/W H'00 H'FF95 Event counter H ECH R H'00 H'FF96 Event counter L ECL R H'00 H'FF97 Clock stop register 2 CKSTP2 R/W H'FF H'FFFB 9.7.2 Register Descriptions 1.
Section 9 Timers Bit 7: Counter overflow flag H (OVH) Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading it when set to 1, then writing 0. When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Section 9 Timers Bit 4: Channel select (CH2) Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a 16-bit event counter which is incremented each time an event clock is input to the AEVL pin as asynchronous event input. In this case, the overflow signal from ECL is selected as the ECH input clock.
Section 9 Timers Bit 2: Count-up enable L (CUEL) Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held. Bit 2 CUEL Description 0 ECL event clock input is disabled ECL value is held 1 ECL event clock input is enabled (initial value) Bit 1: Counter reset control H (CRCH) Bit 1 controls resetting of ECH.
Section 9 Timers 2. Event Counter H (ECH) Bit 7 6 5 4 3 2 1 0 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Section 9 Timers Bit 3: Asynchronous event counter module standby mode control (AECKSTP) Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter. AECKSTP Description 0 Asynchronous event counter is set to module standby mode 1 Asynchronous event counter module standby mode is cleared 9.7.3 (initial value) Operation 1. 16-bit Event Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL, operate as a 16-bit event counter. Figure 9.
Section 9 Timers occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU. 2. 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. Figure 9.21 shows an example of the software processing when ECH and ECL are used as 8-bit event counters. Start Set CH2 to 1 Clear CUEH, CUEL, CRCH, and CRCL to 0 Clear OVH, OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1 End Figure 9.
Section 9 Timers 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21. Table 9.
Section 9 Timers Maximum AEVH/AEVL Pin Input Clock Frequency Mode 16-bit mode H8/3847R Group • When not using the internal step-down circuit VCC = 4.5 to 5.5 V/16 MHz VCC = 2.7 to 5.5 V/10 MHz VCC = 1.8 to 5.5 V/4 MHz • When using the internal step-down circuit VCC = 2.7 to 5.5 V/10 MHz VCC = 1.8 to 5.5 V/4 MHz 8-bit mode Active (high-speed), sleep (high-speed) H8/3847S Group VCC = 2.7 to 3.6 V/10 MHz VCC = 1.8 to 3.6 V/4 MHz H8/38347 Group VCC = 2.7 to 5.5 V/16 MHz H8/38447 Group VCC = 4.5 to 5.
Section 10 Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview This LSI is provided with three serial communication interface (SCI) channels. The functions of the three SCI channels are summarized in table 10.1. Table 10.
Section 10 Serial Communication Interface 10.2 SCI1 10.2.1 Overview Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in synchronous mode. It is also provided with a communication function called a Synchronized Serial Bus (SSB) that enables a number of ICs to be controlled. 1. Features Features of SCI1 are listed below.
Section 10 Serial Communication Interface 2. Block Diagram Figure 10.1 shows a block diagram of SCI1. φ PSS SCK1 SCR1 Transmit/receive control circuit SCSR1 Transfer bit counter SI1 Transfer bit counter φW/4 SDRU SDRL SO1 IRRS1 Legend: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Serial 1 interrupt request flag Prescaler S Figure 10.1 SCI1 Block Diagram Rev. 6.
Section 10 Serial Communication Interface 3. Pin Configuration Table 10.2 shows the SCI1 pin configuration. Table 10.2 SCI1 Pin Configuration Name Abbr. I/O Function SCI1 clock SCK1 I/O SCI1 clock input/output SCI1 data input SI1 Input SCI1 receive data input SCI1 data output SO1 Output SCI1 transmit data output 4. Register Configuration Table 10.3 shows the SCI1 register configuration. Table 10.3 Registers Name Abbr.
Section 10 Serial Communication Interface Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0) Bits 7 and 6 select the operating mode. Bit 7 SNC1 Bit 6 SNC0 Description 0 0 8-bit synchronous mode 0 1 16-bit synchronous mode 1 0 1 1 Continuous clock output mode* 2 Reserved* (initial value) 1 Notes: 1. Use pins SI1 and SO1 as ports. 2. Do not set bits SNC1 and SNC0 to 11. Bit 5: TAIL MARK control (MRKON) Bit 5 controls tail mark output after transfer of 8-bit or 16-bit data.
Section 10 Serial Communication Interface Bit 3: Clock source select 3 (CKS3) Bit 3 selects the clock source to be supplied and sets the SCK1 pin to input or output mode. Bit 3 CKS3 Description 0 Clock source is prescaler S, SCK1 is output pin 1 Clock source is external clock, SCK1 is input pin (initial value) Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0) When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock cycle.
Section 10 Serial Communication Interface Bit 7: Reserved bit Bits 7 is reserved; it is always read as 1 and cannot be modified. Bit 6: Extension data bit (SOL) The SOL bit changes the output level of the SO1 pin. When read, SOL returns the output level of the SO1 pin. After transfer is completed, SO1 pin output retains the value of the last bit of the transmit data, and therefore the SO1 pin output level can be changed by manipulating this bit before or after transmission.
Section 10 Serial Communication Interface Bit 1: Tail mark transmission flag (MTRF) When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit, and cannot be modified. Bit 1 MTRF Description 0 Idle state, or 8-bit/16-bit data transfer in progress 1 Tail mark transmission in progress (initial value) Bit 0: Start flag (STF) The STF bit controls the start of transfer operations. SCI1 transfer operation is started when this bit is set to 1.
Section 10 Serial Communication Interface SDRU read/write operations must only be performed after data transmission/reception has been completed. Data contents are not guaranteed if read/write operations are executed while data transmission/reception is in progress. The value of SDRU is undefined upon reset. 4.
Section 10 Serial Communication Interface Bit 7: SCI1 module standby mode control (S1CKSTP) Bit 7 controls setting and clearing of module standby mode for SCI1. Bit 7 S1CKSTP Description 0 SCI1 is set to module standby mode* 1 SCI1 module standby mode is cleared Note: * 10.2.3 (initial value) Setting to module standby mode resets SCR1, SCSR1, SDRU, and SDRL. Operation Either 8-bit or 16-bit transfer data can be selected as the transfer format.
Section 10 Serial Communication Interface 3. Data Transfer Operations Transmitting: The procedure for transmitting data is as follows. (1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. If necessary, also designate the SO1 pin as an NMOS open-drain output with bit POF1 in PMR2. (2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to CKS0.
Section 10 Serial Communication Interface (5) Read the transfer data from SDRL/SDRU. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL (6) If the serial clock continues to be input after the end of reception, this is regarded as an overrun state, and the ORER flag is set to 1 in SCSR1 (consequently, reception is not performed). Simultaneous transmitting and receiving: The procedure for simultaneously transmitting and receiving data is as follows.
Section 10 Serial Communication Interface 10.2.4 Operation in SSB Mode SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables a number of ICs to be controlled when connected as shown in figure 10.3. In SSB mode, a tail mark is attached and transmitted following an 8-bit or 16-bit data transfer. Either HOLD TAIL or LATCH TAIL can be selected as the tail mark. SCL H8/3847R SCK1 Group chip SO1 IC-A IC-B SDA SCL SDA SCL SDA SCL SDA IC-C Figure 10.
Section 10 Serial Communication Interface SCK1 SO1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 14 Bit 15 Tail mark 1 frame Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1) 3. Tail Mark There are two tail marks: HOLD TAIL and LATCH TAIL. The output waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10.5. Time t in figure 10.5 is determined by the serial clock cycle set by bits CKS2 to CKS0 in SCR1.
Section 10 Serial Communication Interface 4. Transmitting The procedure for transmitting data is as follows. (1) Set SOL to 1 in SCSR1. (2) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. Set POF1 to 1 in PMR2 to designate the SO1 pin as an NMOS open-drain output. (3) Clear SNC1 in SCR1 to 0, and clear or set SNC0 to 0 or 1, to select 8-bit mode or 16-bit mode. Set MRKON to 1 in SCR1 to select SSB mode. (4) Write the transfer data to SDRL/SDRU.
Section 10 Serial Communication Interface 10.2.5 Interrupt Source SCI1 has one interrupt source: transfer completion. When SCI1 completes transfer, IRRS1 is set to 1 in IRR1. The SCI1 interrupt source can be enabled or disabled by the IENS1 bit in IENR1. For details, see section 3.3, Interrupts. 10.2.
Section 10 Serial Communication Interface 10.3 SCI3 10.3.1 Overview In addition to SCI1, this LSI has two serial communication interfaces, SCI3-1 and SCI3-2, with identical functions. In this manual, the generic term SCI3 is used to refer to both of these SCIs. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode.
Section 10 Serial Communication Interface Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length 8 bits Receive error detection Overrun errors • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously.
Section 10 Serial Communication Interface 2. Block Diagram Figure 10.6 shows a block diagram of SCI3.
Section 10 Serial Communication Interface 3. Pin Configuration Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name Abbr. I/O Function SCI3 clock SCK3X I/O SCI3 clock input/output SCI3 receive data input RXD3X Input SCI3 receive data input SCI3 transmit data output TXD3X Output SCI3 transmit data output 4. Register Configuration Table 10.5 shows the SCI3 register configuration. Table 10.5 Registers Name Abbr.
Section 10 Serial Communication Interface 10.3.2 Register Descriptions 1. Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write RSR is a register used to receive serial data. Serial data input to RSR from the RXD3X pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU. 2.
Section 10 Serial Communication Interface 3. Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD3X pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically.
Section 10 Serial Communication Interface 5. Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 COM CHR PE PM STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
Section 10 Serial Communication Interface Bit 5: Parity enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled* 1, 2 Parity bit addition and checking enabled* * 2 (initial value) Notes: 1.
Section 10 Serial Communication Interface Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description 1 stop bit* 2 2 stop bits* 1 0 1 (initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2.
Section 10 Serial Communication Interface Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φ/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate register (BRR). Bit 1 CKS1 Bit 0 CKS0 Description 0 0 φ clock (initial value) *1 0 1 φW /2 clock /φW clock 1 0 φ/16 clock 1 1 φ/64 clock *2 Notes: 1.
Section 10 Serial Communication Interface Bit 7: Transmit interrupt enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0.
Section 10 Serial Communication Interface Bit 5: Transmit enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 TE 0 1 Description Transmit operation disabled* (TXD pin is I/O port) 2 Transmit operation enabled* (TXD pin is transmit data pin) 1 (initial value) Notes: 1. Bit TDRE in SSR is fixed at 1. 2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and serial data transmission is started.
Section 10 Serial Communication Interface Bit 3: Multiprocessor interrupt enable (MPIE) Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Section 10 Serial Communication Interface After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10.12 in 10.3.3,1, Overview.
Section 10 Serial Communication Interface Bit 7: Transmit data register empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Section 10 Serial Communication Interface Bit 5: Overrun error (OER) Bit 5 indicates that an overrun error has occurred during reception. Bit 5 OER 0 1 Description Reception in progress or completed* Clearing condition: After reading OER = 1, cleared by writing 0 to OER 2 An overrun error has occurred during reception* Setting condition: When reception is completed with RDRF set to 1 1 (initial value) Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state.
Section 10 Serial Communication Interface Bit 3: Parity error (PER) Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode.
Section 10 Serial Communication Interface Bit 1: Multiprocessor bit receive (MPBR) Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified.
Section 10 Serial Communication Interface Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) OSC 32.8 kHz Bit Rate (bit/s) n N 38.4 kHz Error (%) n 2 MHz 2.4576 MHz 4 MHz N Error (%) n N Error (%) n N Error (%) n N Error (%) 21 –0.83 — — — 110 Cannot be used, — — — — — — 2 150 as error exceeds 0 3 0 2 12 0.16 3 3 0 2 25 0.
Section 10 Serial Communication Interface Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) OSC 10 MHz 16 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) 110 2 88 –0.25 2 141 0.03 150 2 64 0.16 103 0.16 200 2 48 –0.35 2 77 0.16 250 2 38 0.16 2 62 –0.79 300 — — — 2 51 0.16 600 — — — 2 25 0.16 1200 0 129 0.16 0 207 0.16 2400 0 64 0.16 0 103 0.16 4800 — — — 0 51 0.16 9600 — — — 0 25 0.
Section 10 Serial Communication Interface Notes: 1. φW /2 clock is selected in active (medium- and high-speed) or sleep (medium- and high-speed) mode. 2. φW clock is selected in subactive or subsleep mode. SCI3 can be used only when the φW/2 is selected as the CPU clock in subactive or subsleep mode. 3. The error in table 10.6 is the value obtained from the following equation, rounded to two decimal places. Error (%) = B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10.6.
Section 10 Serial Communication Interface Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) OSC 38.4 kHz 2 MHz 4 MHz Bit Rate (bit/s) n N Error n N Error n N Error 200 0 23 0 — — — — — — 250 — — — — — — 2 124 0 300 2 0 0 — — — — — — 500 — — — — — — 1k 0 249 0 — — — 2.
Section 10 Serial Communication Interface Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) OSC 10 MHz 16 MHz Bit Rate (bit/s) n N Error n N Error 200 — — — — — — 250 — — — 3 124 0 300 — — — — — — 500 — — — 2 249 0 1k — — — 2 124 0 2.
Section 10 Serial Communication Interface Notes: The value set in BRR is given by the following equation: OSC N= —1 2n (8 × 2 × B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) OSC: Value of φOSC (Hz) n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 10.10.) Table 10.10 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 0 2 3 φ 1 2 φW /2* /φW * φ/16 φ/64 0 0 1 1 0 1 0 1 Notes: 1.
Section 10 Serial Communication Interface 9. Clock Stop Register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Section 10 Serial Communication Interface Bits 7 to 6: Reserved bits Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. Bit 5: P42/TXD32 pin function switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32 Description 0 Functions as P42 I/O pin 1 Note: (initial value) Functions as TXD32 output pin* * Set the TE bit in SCR3 after setting this bit to 1.
Section 10 Serial Communication Interface Bit 2: RXD32 pin input data inversion switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted. Bit 2 SCINV2 Description 0 RXD32 input data is not inverted 1 RXD32 input data is inverted (initial value) Bit 1: TXD31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted.
Section 10 Serial Communication Interface 10.3.3 Operation 1. Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.11.
Section 10 Serial Communication Interface Table 10.
Section 10 Serial Communication Interface Table 10.
Section 10 Serial Communication Interface c. Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.13. Table 10.
Section 10 Serial Communication Interface RDR RDR RSR (reception in progress) RSR↑ (reception completed, transfer) RXD3x pin RXD3x pin RDRF ← 1 (RXI request when RIE = 1) RDRF = 0 Figure 10.7 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmission in progress) TSR↓ (transmission completed, transfer) TXD3x pin TXD3x pin TDRE ← 1 (TXI request when TIE = 1) TDRE = 0 Figure 10.
Section 10 Serial Communication Interface 2. Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Section 10 Serial Communication Interface Table 10.
Section 10 Serial Communication Interface b. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3X pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection. When an external clock is input at the SCK3X pin, the clock frequency should be 16 times the bit rate.
Section 10 Serial Communication Interface Figure 10.10 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Set data transfer format in SMR 3 Set value in BRR 1. Set clock selection in SCR3. Be sure to clear the other bits to 0. If clock output is selected in asynchronous mode, the clock is output immediately after setting bits CKE1 and CKE0.
Section 10 Serial Communication Interface • Transmitting Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data to TDR 2 Continue data transmission? Yes 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR.
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD3x pin using the relevant data transfer format in table 10.14. When the stop bit is sent, SCI3 checks bit TDRE.
Section 10 Serial Communication Interface • Receiving Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bits OER, PER, FER in SSR OER + PER + FER = 1? 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. Yes 2. Read SSR and check that bit RDRF is set to 1.
Section 10 Serial Communication Interface 4 Start receive error processing Overrun error processing OER = 1? Yes No FER = 1? Break? Yes No No PER = 1? Yes 4. If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Yes Reception cannot be resumed if any of these bits is set to 1.
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.14. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
Section 10 Serial Communication Interface Figure 10.14 shows an example of the operation when receiving in asynchronous mode. Start bit Serial data 1 0 Receive data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 1 frame Receive data D0 D1 Parity Stop bit bit D7 0/1 0 Mark state (idle state) 1 1 frame RDRF FER RXI request LSI operation User processing RDRF cleared to 0 RDR data read 0 start bit detected ERI request in response to framing error Framing error processing Figure 10.
Section 10 Serial Communication Interface a. Data transfer format The general data transfer format in synchronous communication is shown in figure 10.15. * * Serial clock LSB Serial data Bit 0 Don't care MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care 8 bits One transfer data unit (character or frame) Note: * High level except in continuous transmission/reception Figure 10.
Section 10 Serial Communication Interface c. Data transfer operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10.10. • Transmitting Figure 10.16 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Rev. 6.
Section 10 Serial Communication Interface Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR No TDRE = 1? Yes 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. Write transmit data to TDR 2 Continue data transmission? 1.
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. When clock output mode is selected, SCI3 outputs 8 serial clock pulses.
Section 10 Serial Communication Interface • Receiving Figure 10.18 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bit OER in SSR 1. Read bit OER in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Yes OER = 1? 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR.
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Section 10 Serial Communication Interface • Simultaneous transmit/receive Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Section 10 Serial Communication Interface 4. Multiprocessor Communication Function The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). In multiprocessor communication, each receiver is assigned its own ID code.
Section 10 Serial Communication Interface Sender Communication line Serial data Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) H'01 (MPB = 1) ID transmission cycle (specifying the receiver) H'AA (MPB = 0) Data transmission cycle (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit Figure 10.
Section 10 Serial Communication Interface Start Sets bits SPC31 and SPC32 to 1 in SPCR 1 Read bit TDRE in SSR TDRE = 1? No 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. Yes Set bit MPDT in SSR 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0.
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14. When the stop bit is sent, SCI3 checks bit TDRE.
Section 10 Serial Communication Interface Start 1 2 1. Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 2. Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. Read bits OER and FER in SSR OER + FER = 1? 3. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR and compare it with this receiver's own ID.
Section 10 Serial Communication Interface Start receive error processing Overrun error processing OER = 1? Yes Yes No FER = 1? No Break? Yes No Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing (A) Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.25 shows an example of the operation when receiving using the multiprocessor format. Rev. 6.
Section 10 Serial Communication Interface Start bit Serial data 1 0 Receive data (ID1) D0 D1 MPB D7 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RXI request MPIE cleared to 0 RDRF cleared to 0 User processing No RXI request RDR retains previous state RDR data read When data is not this receiver's ID, bit MPIE is set to 1 again (a) When data does not match this receiver's
Section 10 Serial Communication Interface 10.3.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.16. Table 10.16 SCI3 Interrupt Requests Interrupt Abbr.
Section 10 Serial Communication Interface For further details, see section 3.3, Interrupts. 10.3.5 Application Notes The following points should be noted when using SCI3. 1. Relation between Writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Section 10 Serial Communication Interface 3. Break Detection and Processing When a framing error is detected, a break can be detected by reading the value of the RXD3X pin directly. In a break, the input from the RXD3X pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4.
Section 10 Serial Communication Interface 16 clock pulses 8 clock pulses 0 7 15 0 7 15 0 Internal basic clock Receive data (RXD3x) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). M ={(0.5 – 1 ) – D – 0.5 – (L – 0.5) F} × 100 [%] N 2N where .....
Section 10 Serial Communication Interface 7. Relation between RDR Reads and Bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically.
Section 10 Serial Communication Interface 9. Cautions on Switching of SCK3X Pin Function If the function of the SCK3X pin is switched from clock output to I/O port after using the SCI3 in clock synchronization mode, the “low” level is output in a moment (1/2 of the system clock φ) at the SCK3X pin function switching. This momentary “low” level output can be avoided in either of the following two methods: a.
Section 11 14-Bit PWM Section 11 14-Bit PWM 11.1 Overview This LSI is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows.
Section 11 14-Bit PWM 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the 14-bit PWM. PWDRU φ/2 φ/4 φ/8 φ/16 PWM waveform generator Internal data bus PWDRL PWCR PWM Legend: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11.1 Block Diagram of the 14 bit PWM 11.1.3 Pin Configuration Table 11.1 shows the output pin assigned to the 14-bit PWM. Table 11.1 Pin Configuration Name Abbr.
Section 11 14-Bit PWM 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 14-bit PWM. Table 11.2 Register Configuration Name Abbr. R/W Initial Value Address PWM control register PWCR W H'FC H'FFD0 PWM data register U PWDRU W H'C0 H'FFD1 PWM data register L PWDRL W H'00 H'FFD2 Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB 11.2 Register Descriptions 11.2.
Section 11 14-Bit PWM Bits 1 and 0: Clock select 1 and 0 (PWCR1, PWCR0) Bits 1 and 0 select the clock supplied to the 14-bit PWM. These bits are write-only bits; they are always read as 1.
Section 11 14-Bit PWM 11.2.
Section 11 14-Bit PWM 11.2.3 Clock Stop Register 2 (CKSTPR2) Bit 7 6 5 4 — — — — 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — R/W R/W R/W R/W AECKSTP WDCKSTP PWCKSTP LDCKSTP CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the PWM is described here. For details of the other bits, see the sections on the relevant modules.
Section 11 14-Bit PWM 11.3 Operation 11.3.1 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P30/PWM is designated for PWM output. 2. Set bits PWCR1 and PWCR0 in the PWM control register (PWCR) to select a conversion period of 131,072/φ (PWCR1 = 1, PWCR0 = 1), 65,536/φ (PWCR1 = 1, PWCR0 = 0), 32,768/φ (PWCR1 = 0, PWCR0 = 1), or 16,384/φ (PWCR1 = 0, PWCR0 = 0). 3.
Section 11 14-Bit PWM 1 conversion period t f1 t H1 t f2 t f63 t H2 t H3 t f64 t H63 t H64 TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f64 Figure 11.2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11.3. Table 11.
Section 12 A/D Converter Section 12 A/D Converter 12.1 Overview This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 12 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution • 12 input channels • Conversion time: approx. 12.
Section 12 A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AN 8 AN 9 AN 10 AN 11 Multiplexer ADSR AVCC + Comparator – AVCC Reference voltage Control logic AVSS AVSS ADRRH ADRRL Legend: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag Figure 12.1 Block Diagram of the A/D Converter Rev. 6.
Section 12 A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr.
Section 12 A/D Converter 12.2 Register Descriptions 12.2.
Section 12 A/D Converter Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Conversion Time (Active (High-Speed) Mode)* Bit 7 CKS Conversion Period φ = 1 MHz φ = 5 MHz 0 62/φ (initial value) 62 µs 12.4 µs 1 31/φ 31 µs — Note: * For information on conversion time settings for which operation is guaranteed, see section 15, Electrical Characteristics. Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input.
Section 12 A/D Converter Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0.
Section 12 A/D Converter Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF Description 0 Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion 1 Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.
Section 12 A/D Converter 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1.
Section 12 A/D Converter 12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12.3. Table 12.3 A/D Converter Operation Modes Operation Mode Reset Active Subactive Subsleep Standby Module Standby AMR Reset Functions Functions Held Held Held Held Held ADSR Reset Functions Functions Held Held Held Held Held ADRRH Held* Functions Functions Held Held Held Held Held ADRRL Held* Functions Functions Held Held Held Held Held Note: 12.
Section 12 A/D Converter 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 to 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) Rev. 6.
Section 12 A/D Converter Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) 12.6 Application Notes 12.6.
Section 12 A/D Converter • In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not used, it is recommended that AVCC be connected to the system power supply and the ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop register 1 (CKSTPR1). 12.6.
Section 12 A/D Converter Rev. 6.
Section 13 LCD Controller/Driver Section 13 LCD Controller/Driver 13.1 Overview This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features Features of the LCD controller/driver are given below.
Section 13 LCD Controller/Driver 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the LCD controller/driver.
Section 13 LCD Controller/Driver 13.1.3 Pin Configuration Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr.
Section 13 LCD Controller/Driver 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR) Bit 7 6 5 4 3 2 1 0 DTS1 DTS0 CMX SGX SGS3 SGS2 SGS1 SGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. LPCR is initialized to H'00 upon reset.
Section 13 LCD Controller/Driver Bit 4: Expansion Signal Selection (SGX) Bit 4 (SGX) selects whether the SEG40/CL1, SEG39/CL2, SEG38/DO, and SEG37/M pins are used as segment pins (SEG40 to SEG37) or as segment external expansion signal pins (CL1, CL2, DO, and M). In the H8/38347 Group and H8/38447 Group this bit should be left at its initial value and not written to. Changing the value of this bit may prevent the SEG/COM signal from operating normally.
Section 13 LCD Controller/Driver 13.2.2 LCD Control Register (LCR) Bit 7 6 5 4 3 2 1 0 — PSW ACT DISP CKS3 CKS2 CKS1 CKS0 Initial value 1 0 0 0 0 0 0 0 Read/Write — R/W R/W R/W R/W R/W R/W R/W LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset. Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1 and cannot be modified.
Section 13 LCD Controller/Driver Bit 4: Display data control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description 0 Blank data is displayed 1 LCD RAM data is display (initial value) Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Section 13 LCD Controller/Driver 13.2.3 LCD Control Register 2 (LCR2) Bit 7 6 5 4 3 2 1 0 DTS1 DTS0 CMX SGX SGS3 SGS2 SGS1 SGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform, and selects the duty cycle of the charge/discharge pulses which control disconnection of the power supply split-resistance from the power supply circuit.
Section 13 LCD Controller/Driver Bits 3 to 0: Charge/discharge pulse duty cycle select (CDS3 to CDS0) Bit 3 CDS3 Bit 2 CDS2 Bit 1 CDS1 Bit 0 CDS0 Duty Cycle Notes 0 0 0 0 1 Fixed high 0 0 0 1 1/8 0 0 1 0 2/8 0 0 1 1 3/8 0 1 0 0 4/8 0 1 0 1 5/8 0 1 1 0 6/8 0 1 1 1 0 1 0 * * 1/16 1 1 * * 1/32 (initial value) Fixed low *: Don’t care Bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power supply circuit.
Section 13 LCD Controller/Driver 13.2.4 Clock Stop Register 2 (CKSTPR2) Bit 7 6 5 4 — — — — 3 2 1 0 AECKSTP WDCKSTP PWCKSTP LDCKSTP Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — R/W R/W R/W R/W CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the LCD controller/driver is described here. For details of the other bits, see the sections on the relevant modules.
Section 13 LCD Controller/Driver 13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. 1. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.3. VCC V0 V1 V2 V3 VSS Figure 13.3 Handling of LCD Drive Power Supply when Using 1/2 Duty b.
Section 13 LCD Controller/Driver d. LCD drive power supply setting With this LSI, there are two ways of providing LCD power: by using the on-chip power supply circuit, or by using an external circuit. When the on-chip power supply circuit is used for the LCD drive power supply, the V0 and V1 pins should be interconnected externally, as shown in figure 13.4 (a).
Section 13 LCD Controller/Driver 2. Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. c. Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification.
Section 13 LCD Controller/Driver 13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles with the segment not externally expanded are shown in figures 13.5 to 13.8, and ones with the segments externally expanded are shown in figures 13.9 to 13.12.
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 H'F740 SEG2 SEG2 H'F753 SEG40 COM3 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG1 SEG1 SEG1 SEG40 SEG40 SEG39 SEG39 SEG39 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) Rev. 6.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Display space SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 H'F74A Space not used for display H'F753 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) Rev. 6.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Display space SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 H'F745 Space not used for display H'F753 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode) Rev. 6.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 Expansion driver display space H'F75F SEG64 SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 SEG63 COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 13.9 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” 1/4 duty) Rev. 6.
Section 13 LCD Controller/Driver Bit 7 H'F740 Bit 6 Bit 5 Bit 4 SEG2 SEG2 SEG2 Bit 3 Bit 2 Bit 1 Bit 0 SEG1 SEG1 SEG1 Expansion driver display space H'F75F SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.10 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” 1/3 duty) Rev. 6.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Expansion driver display space H'F75F SEG128 SEG128 SEG127 SEG127 SEG126 SEG126 SEG125 SEG125 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Figure 13.11 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” 1/2 duty) Rev. 6.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 Expansion driver display space H'F75F SEG256 SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 Figure 13.12 LCD RAM Map with Segment Externally Expanded (SGX = “1”, SGS3 to SGS0 = “0000” static) Rev. 6.
Section 13 LCD Controller/Driver 13.3.3 Luminance Adjustment Function (V0 Pin) Figure 13.13 shows a detailed block diagram of the LCD drive power supply unit. The voltage output to the V0 pin is VCC. When this voltage is used directly as the LCD drive power supply, the V0 and V1 pins should be shorted. Also, connecting a variable resistance, R, between the V0 and V1 pins makes it possible to adjust the voltage applied to the V1 pin, and so to provide luminance adjustment for the LCD panel.
Section 13 LCD Controller/Driver 13.3.4 Low-Power-Consumption LCD Drive System The use of the built-in split-resistance is normally the easiest method for implementing the LCD power supply circuit, but since the built-in resistance is fixed, a certain direct current flows constantly from the built-in resistance’s VCC to VSS. As this current does not depend on the current dissipation of the LCD panel, if an LCD panel with a small current dissipation is used, a wasteful amount of power will be consumed.
Section 13 LCD Controller/Driver 5. As can be seen from the above description, the capacitances and charging/discharging periods of the capacitors are determined by the current dissipation of the LCD panel used. The charging/discharging periods can be selected with bits CDS3 to CDS0. 6. The actual capacitor capacitances and charging/discharging periods must be determined experimentally in accordance with the current dissipation requirements of the LCD panel.
Section 13 LCD Controller/Driver 1 frame 1 frame M M Data Data V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS V1 V2 V3 VSS COM4 SEGn V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame M M Data Data COM1 V1 V2, V3 VSS COM1 COM2 V1 V2, V3 VSS SEGn SEGn V1 VSS V1 VSS (d) Waveform with static output (c) Waveform with 1/2 duty Figure 13.
Section 13 LCD Controller/Driver 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 COM4 V1 V2 V3 VSS SEGn 1 frame 1 frame 1 frame 1 frame V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 V1 V2 V3 VSS SEGn (a) Waveform with 1/4 duty 1 frame 1 frame (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data V1 COM1 V1 V2, V3 VSS COM1 COM2 V1 V2, V3 VSS SEGn SEGn V1 V2, V
Section 13 LCD Controller/Driver Table 13.3 Output Levels Data 0 0 1 1 M 0 1 0 1 Common output V1 VSS V1 VSS Segment output V1 VSS VSS V1 Common output V2, V3 V2, V3 V1 VSS Segment output V1 VSS VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Static 1/2 duty 1/3 duty 1/4 duty 13.3.
Section 13 LCD Controller/Driver 13.3.6 Boosting the LCD Drive Power Supply When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case, the power supply impedance must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 13.17, or by adding a split-resistance externally. VCC V0 V1 R This LSI R = several kΩ to several MΩ V2 R C= 0.1 to 0.3µF V3 R VSS Figure 13.
Section 13 LCD Controller/Driver 13.3.7 Connection to HD66100 If the segments are to be expanded externally, an HD66100 should be connected. Connecting one HD66100 provides 80-segment expansion. When carrying out external expansion, select the external expansion signal function of pins SEG40 to SEG37 with the SGX bit in LPCR, and set bits SGS3 to SGS0 to 0000. Data is output externally from SEG1 of the LCD RAM. SEG36 to SEG1 function as ports. Figure 13.18 shows examples of connection to an HD66100.
Section 13 LCD Controller/Driver VCC VCC V0 V1 V2 V3 This LSI V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M VSS SEG40/CL1 SEG39/CL2 SEG38/DO SEG37/M HD66100 (a) 1/3 bias, 1/4 duty or 1/3 duty VCC VCC V0 V1 V2 V3 This LSI V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M VSS SEG40/CL1 SEG39/CL2 SEG38/DO SEG37/M HD66100 (b) 1/2 duty VCC VCC V0 V1 V2 V3 This LSI V1 V4 V3 V2 GND VEE SHL CL1 CL2 DI M VSS SEG40/CL1 SEG39/CL2 SEG38/DO SEG37/M (c) Static Figure 13.18 Connection to HD66100 Rev. 6.
Section 14 Power Supply Circuit Section 14 Power Supply Circuit 14.1 Overview H8/3847R Group, H8/38347 Group and H8/38447 Group incorporate an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V to 3.2 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.
Section 14 Power Supply Circuit 14.3 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the CVCC pin and VCC pin, as shown in figure 14.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 1.8 V to 5.5 V for the H8/3847R Group and 2.7 V to 3.6 V for the H8/38347 Group and H8/38447 Group.
Section 15 Electrical Characteristics Section 15 Electrical Characteristics 15.1 H8/3847R Group Absolute Maximum Ratings (Regular Specifications) Table 15.1 lists the absolute maximum ratings. Table 15.1 Absolute Maximum Ratings Item Symbol Value Unit Notes *1 Power supply voltage VCC –0.3 to +7.0 V Analog power supply voltage AVCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +13.0 V Input voltage Ports other than Ports B and C Vin –0.3 to VCC +0.
Section 15 Electrical Characteristics 15.2 H8/3847R Electrical Characteristics (Regular Specifications) 15.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range of the H8/3847R Group are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 38.4 fW (kHz) fosc (MHz) 16.0 10.0 32.768 4.0 2.0 1.8 2.7 4.5 5.5 1.
Section 15 Electrical Characteristics 2. Power supply voltage and operating frequency range φ (MHz) 8.0 5.0 19.2 2.0 16.384 1.0 (0.5) 4.5 5.5 VCC (V) Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used. When using an oscillator, the minimum operating frequency is φ=1MHz. 9.6 φSUB (kHz) 2.7 1.8 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Internal power supply step-down circuit not used 8.192 4.8 4.096 1000 φ (kHz) 1.
Section 15 Electrical Characteristics 3. Analog power supply voltage and A/D converter operating range 1000 φ (kHz) φ (MHz) 5.0 625 500 1.0 0.5 1.8 2.7 4.5 1.8 5.5 2.7 4.5 5.5 AVCC (V) AVCC (V) • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • Internal power supply step-down circuit • Internal power supply step-down circuit not used φ (kHz) not used and used 625 500 1.8 2.7 4.5 5.
Section 15 Electrical Characteristics 15.2.2 DC Characteristics Table 15.2 lists the DC characteristics. Table 15.2 DC Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*4 (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Input VIH high voltage Min Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0 to IRQ4, AEVL, AEVH, TMIC, TMIF, 0.8 VCC — VCC + 0.3 V TMIG, SCK1, SCK31, SCK32, ADTRG 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Input VIL low voltage Min Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0 to IRQ4, AEVL, AEVH, TMIC, TMIF, –0.3 — 0.2 VCC V TMIG, SCK1, SCK31, SCK32, ADTRG –0.3 — 0.1 VCC — 0.3 VCC –0.3 — 0.2 VCC –0.3 — 0.2 V Internal power supply step-down circuit used –0.3 — 0.2 VCC V VCC = 4.0 V to 5.5 V V VCC = 4.0 V to 5.5 V Except the above –0.3 — 0.1 VCC –0.3 — 0.1 VCC V VCC = 1.8 V to 5.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Input/ | IIL | output leakage current Min Typ Max Unit Test Condition Notes — — 20.0 µA VIN = 0.5 V to *2 — — 1.0 VCC – 0.5 V *1 OSC1, X1, P10 to P17, — P20 to P27, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 — 1.0 PB0 to PB7, PC0 to PC3 — 1.0 RES, P43 — µA VIN = 0.5 V to VCC – 0.5 V VIN = 0.5 V to AVCC – 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition — 15 30 µA *3 VCC = 2.7 V, LCD on 5 * 32 kHz crystal oscillator (φSUB = φW/2) *6 — 8 — µA *3 VCC = 2.7 V, LCD on *5 32 kHz crystal oscillator (φSUB = φW/8) Reference value *6 VCC — 7.5 16 µA *3 VCC = 2.7 V, LCD on *5 32 kHz crystal oscillator (φSUB = φW/2) *6 Watch IWATCH mode current dissipation VCC — 2.8 6.0 µA VCC = 2.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Allow- –IOH able output high current (per pin) All output pins Allow- ∑ – IOH able output high current (total) All output pins Min Typ Max Unit Test Condition — — 2.0 mA — — 0.2 — — 15.0 — — 10.0 Notes VCC = 4.0 V to 5.5 V Except the above mA VCC = 4.0 V to 5.5 V Except the above Notes: Connect the TEST pin to VSS. 1. Applies to the Mask ROM products. 2. Applies to the HD6473847R. 3.
Section 15 Electrical Characteristics 15.2.3 AC Characteristics Table 15.3 lists the control signal timing, and tables 15.4 and 15.5 list the serial interface timing. Table 15.3 Control Signal Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*4 (including subactive mode) unless otherwise indicated.
Section 15 Electrical Characteristics Item External clock high width External clock low width External clock rise time External clock fall time Values Applicable Symbol Pins Min Typ Max Unit Test Condition tCPH 25 — — ns VCC = 4.5 V to 5.5 V Figure 15.1 *2 40 — — tCPL tCPr tCPf OSC1 Reference Figure VCC = 2.7 V to 5.5 V Figure 15.1 100 — — X1 — 15.26 or 13.02 — µs VCC = 1.8 V to 5.5 V OSC1 25 — — ns 40 — — VCC = 4.5 V to 5.5 V Figure 15.1 *2 VCC = 2.7 V to 5.
Section 15 Electrical Characteristics Item Input pin low width Applicable Symbol Pins tIL UD pin minimum tUDH modulation width tUDL Notes: 1. 2. 3. 4. Values Min Typ Max Unit IRQ0 to IRQ4, 2 WKP0 to WKP7, ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH — — tcyc UD — 4 Test Condition Reference Figure Figure 15.3 tsubcyc — tcyc Figure 15.4 tsubcyc Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). When internal power supply step-down circuit is not used.
Section 15 Electrical Characteristics Table 15.4 Serial Interface (SCI1) Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2 unless otherwise indicated Item Applicable Symbol Pins Values Min Typ Max Unit Test Condition Reference Figure Input clock cycle tScyc SCK1 4 — — tcyc Figure 15.5 Input clock high width tSCKH SCK1 0.4 — — tScyc Figure 15.5 Input clock low width tSCKL SCK1 0.4 — — tScyc Figure 15.
Section 15 Electrical Characteristics Table 15.5 Serial Interface (SCI3-1, SCI3-2) Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2 (including subactive mode) unless otherwise indicated. Values Item Symbol Min Typ Max Unit Input clock Asynchronous tScyc 4 — — tcyc or cycle Synchronous 6 — — tsubcyc Input clock pulse width tSCKW 0.4 — 0.
Section 15 Electrical Characteristics 15.2.4 A/D Converter Characteristics Table 15.6 shows the A/D converter characteristics. Table 15.6 A/D Converter Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*6 unless otherwise indicated.
Section 15 Electrical Characteristics 15.2.5 LCD Characteristics Table 15.7 shows the LCD characteristics. Table 15.7 LCD Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*3 (including subactive mode) unless otherwise indicated. Item Symbol Applicable Values Pins Min Typ Max Unit Segment driver VDS drop voltage SEG1 to SEG40 — — 0.6 V Common driver VDC drop voltage COM1 to COM4 — — 0.3 V 0.5 3.0 9.0 MΩ 2.2 — 5.
Section 15 Electrical Characteristics Table 15.8 Segment External Expansion AC Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2 (including subactive mode) unless otherwise indicated. Item Symbol Values Applicable Pins Min Clock high width tCWH CL1, CL2 Clock low width Clock setup time tCWL tCSU CL2 CL1, CL2 800.0 800.0 500.0 Typ Max Reference Test Unit Conditions Figure — ns *1 Figure 15.8 ns *1 Figure 15.8 ns *1 Figure 15.8 Figure 15.
Section 15 Electrical Characteristics 15.3 H8/3847R Group Absolute Maximum Ratings (Wide-range Specification) Table 15.9 lists the absolute maximum ratings. Table 15.9 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +7.0 V Analog power supply voltage AVCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +13.0 V Input voltage Ports other than Ports B and C Vin –0.3 to VCC +0.3 V Ports B and C AVin –0.3 to AVCC +0.
Section 15 Electrical Characteristics 15.4 H8/3847R Electrical Characteristics (Wide-range Specification) 15.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range 38.4 fW (kHz) fosc (MHz) 16.0 10.0 32.768 4.0 2.0 1.8 2.7 4.5 5.5 1.8 5.5 VCC (V) VCC (V) • Active (high-speed) mode 3.
Section 15 Electrical Characteristics 2. Power supply voltage and operating frequency range φ (MHz) 8.0 5.0 19.2 2.0 16.384 1.0 (0.5) 4.5 5.5 VCC (V) Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used. When using an oscillator, the minimum operating frequency is φ=1MHz. 9.6 φSUB (kHz) 2.7 1.8 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Internal power supply step-down circuit not used 8.192 4.8 4.096 1000 φ (kHz) 1.
Section 15 Electrical Characteristics 3. Analog power supply voltage and A/D converter operating range 1000 φ (kHz) φ (MHz) 5.0 625 500 1.0 0.5 1.8 2.7 4.5 1.8 5.5 2.7 4.5 5.5 AVCC (V) AVCC (V) • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode • Internal power supply step-down circuit • Internal power supply step-down circuit not used φ (kHz) not used and used 625 500 1.8 2.7 4.5 5.
Section 15 Electrical Characteristics 15.4.2 DC Characteristics Table 15.10 lists the DC characteristics. Table 15.10 DC Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Input VIH high voltage Min Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0 to IRQ4, AEVL, AEVH, TMIC, TMIF, 0.8 VCC — VCC + 0.3 V TMIG, SCK1, SCK31, SCK32, ADTRG 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Input VIL low voltage Min Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0 to IRQ4, AEVL, AEVH, TMIC, TMIF, –0.3 — 0.2 VCC V TMIG, SCK1, SCK31, SCK32, ADTRG –0.3 — 0.1 VCC — 0.3 VCC –0.3 — 0.2 VCC –0.3 — 0.2 V Internal power supply step-down circuit used –0.3 — 0.2 VCC V VCC = 4.0 V to 5.5 V Output VOL low voltage V VCC = 4.0 V to 5.5 V Except the above –0.3 — 0.1 VCC –0.3 — 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Input/ | IIL | output leakage current Min Typ Max Unit Test Condition Notes — — 20.0 µA VIN = 0.5 V to *2 — — 1.0 VCC – 0.5 V *1 OSC1, X1, P10 to P17, — P20 to P27, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 — 1.0 PB0 to PB7, PC0 to PC3 — 1.0 RES, P43 — µA VIN = 0.5 V to VCC – 0.5 V VIN = 0.5 V to AVCC – 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition — 15 30 µA *3 VCC = 2.7 V, LCD on 4 * 32 kHz crystal oscillator (φSUB = φW/2) *5 — 8 — µA *3 VCC = 2.7 V, LCD on *4 32 kHz crystal oscillator (φSUB = φW/8) Reference value *5 VCC — 7.5 16 µA *3 VCC = 2.7 V, LCD on *4 32 kHz crystal oscillator (φSUB = φW/2) *5 Watch IWATCH mode current dissipation VCC — 2.8 6.0 µA VCC = 2.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Allow- –IOH able output high current (per pin) All output pins Allow- ∑ – IOH able output high current (total) All output pins Min Typ Max Unit Test Condition — — 2.0 mA — — 0.2 — — 15.0 — — 10.0 Notes VCC = 4.0 V to 5.5 V Except the above mA VCC = 4.0 V to 5.5 V Except the above Notes: Connect the TEST pin to VSS. 1. Applies to the Mask ROM products. 2. Applies to the HD6473847R. 3.
Section 15 Electrical Characteristics 15.4.3 AC Characteristics Table 15.11 lists the control signal timing, and tables 15.12 and 15.13 list the serial interface timing. Table 15.11 Control Signal Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated.
Section 15 Electrical Characteristics Item External clock high width External clock low width External clock rise time External clock fall time Values Applicable Symbol Pins Min Typ Max Unit Test Condition tCPH 25 — — ns VCC = 4.5 V to 5.5 V Figure 15.1 *2 40 — — VCC = 2.7 V to 5.5 V Figure 15.1 tCPL tCPr tCPf OSC1 100 — — X1 — 15.26 or 13.02 — µs OSC1 25 — — ns 40 — — Reference Figure VCC = 1.8 V to 5.5 V 100 — — X1 — 15.26 or 13.
Section 15 Electrical Characteristics Item Input pin low width Applicable Symbol Pins tIL UD pin minimum tUDH modulation width tUDL Values Min Typ Max Unit IRQ0 to IRQ4, 2 WKP0 to WKP7, ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH — — tcyc UD — 4 Test Condition Reference Figure Figure 15.3 tsubcyc — tcyc Figure 15.4 tsubcyc Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 2. When internal power supply step-down circuit is not used. 3.
Section 15 Electrical Characteristics Table 15.12 Serial Interface (SCI1) Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated Applicable Symbol Pins Item Values Min Typ Max Unit Test Condition Reference Figure Input clock cycle tScyc SCK1 4 — — tcyc Figure 15.5 Input clock high width tSCKH SCK1 0.4 — — tScyc Figure 15.5 Input clock low width tSCKL SCK1 0.4 — — tScyc Figure 15.
Section 15 Electrical Characteristics Table 15.13 Serial Interface (SCI3-1, SCI3-2) Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated. Values Item Symbol Min Typ Max Unit Input clock Asynchronous tScyc 4 — — tcyc or cycle Synchronous 6 — — tsubcyc Input clock pulse width tSCKW 0.4 — 0.
Section 15 Electrical Characteristics 15.4.4 A/D Converter Characteristics Table 15.14 shows the A/D converter characteristics. Table 15.14 A/D Converter Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated.
Section 15 Electrical Characteristics 15.4.5 LCD Characteristics Table 15.15 shows the LCD characteristics. Table 15.15 LCD Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated. Item Symbol Applicable Values Pins Min Typ Max Unit Segment driver VDS drop voltage SEG1 to SEG40 — — 0.6 V Common driver VDC drop voltage COM1 to COM4 — — 0.3 V 0.5 3.0 9.0 MΩ 2.2 — 5.
Section 15 Electrical Characteristics Table 15.16 Segment External Expansion AC Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C (including subactive mode) unless otherwise indicated. Item Symbol Applicable Values Pins Min Clock high width tCWH CL1, CL2 800.0 — — ns * Figure 15.8 Clock low width tCWL CL2 800.0 — — ns * Figure 15.8 Clock setup time tCSU CL1, CL2 500.0 — — ns * Figure 15.
Section 15 Electrical Characteristics 15.5 H8/3847S Group Absolute Maximum Ratings Table 15.17 lists the absolute maximum ratings. Table 15.17 Absolute Maximum Ratings Item Symbol Value Unit Notes V *1 Power supply voltage VCC –0.3 to +4.3 Analog power supply voltage AVCC –0.3 to +4.3 V Input voltage Ports other than Port B, C Vin –0.3 to VCC +0.3 V Port B, C AVin –0.3 to AVCC +0.
Section 15 Electrical Characteristics 15.6 H8/3847S Group Electrical Characteristics 15.6.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. 1. Power supply voltage and oscillator frequency range fW (kHz) fosc (MHz) 38.4 10.0 32.768 4.0 2.0 1.8 2.7 3.6 1.8 VCC (V) VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode Note: fosc is the oscillator frequency.
Section 15 Electrical Characteristics φ (MHz) 2. Power supply voltage and operating frequency range 5.0 19.2 2.0 16.384 1.0 (0.5) 1.8 2.7 3.6 9.6 Note: Figures in parentheses are the minimum operating frequency of a case external clocks are used. When using an oscillator, the minimum operating frequency is φ=1MHz. φSUB (kHz) VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 8.192 4.8 4.096 φ (kHz) 1.8 3.
Section 15 Electrical Characteristics 15.6.2 DC Characteristics Table 15.18 lists the DC characteristics. Table 15.18 DC Characteristics Values Item Symbol Applicable Pins Input high voltage VIH Input low VIL voltage Output high voltage VOH Min Typ Max Unit Test Condition 0.9 VCC — VCC + 0.3 V SI1, RXD31, RXD32, UD 0.8 VCC — VCC + 0.3 V OSC1 0.9 VCC — VCC + 0.3 V X1 RES, WKP0 to WKP7, IRQ0 to IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, SCK1, SCK31, SCK32, ADTRG 0.9 VCC — VCC + 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Output low voltage VOL output leakage current | IIL | Typ Max Unit Test Condition P10 to P17, P40 to P42 — Min — 0.5 V P50 to P57, P60 to P67, — P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 — 0.5 IOL = 0.4 mA P20 to P27, P30 to P37 — — 0.5 IOL = 0.4 mA RES, — OSC1, X1, P10 to P17, P20 to P27, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 — 1.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Active mode current dissipation IOPE2 — 0.1 *3 Active (mediumspeed) mode VCC = 1.8 V, fOSC = 2 MHz φOSC/128 — 0.3 *3 Active (mediumspeed) mode VCC = 3 V, fOSC = 4 MHz φOSC/128 — 0.7 1.6 Active (mediumspeed) mode VCC = 3 V, fOSC = 10 MHz φOSC/128 — 0.2 *3 — 0.6 *3 VCC = 3 V, fOSC = 4 MHz — 1.4 2.9 VCC = 3 V, fOSC = 10 MHz — 8 *3 — 4 *3 VCC = 2.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH — 1.4 *3 µA *1 *2 — 2.2 *3 VCC = 2.7 V, Ta = 25°C 32 kHz crystal oscillator LCD not used — 2.8 6 VCC = 2.7 V, 32 kHz crystal oscillator LCD not used — 0.3 *3 — 0.5 *3 Stand-by ISTBY mode current dissipation VCC VCC µA VCC = 1.8 V, Ta = 25°C 32 kHz crystal oscillator LCD not used 32 kHz crystal oscillator not used VCC = 1.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Allowable ∑ – IOH output high current (total) All output pins Min Typ Max Unit Test Condition — — 10.0 mA Notes Notes: Connect the TEST pin to VSS. 1. Pin States during Current Dissipation Measurement.
Section 15 Electrical Characteristics 15.6.3 AC Characteristics Table 15.19 lists the control signal timing, and tables 15.20 and 15.21 list the serial interface timing. Table 15.19 Control Signal Timing Item System clock oscillation frequency Applicable Symbol Pins fOSC OSC clock (φOSC) tOSC cycle time Values Typ Max Unit Test Condition OSC1, OSC2 2 — 10 MHz VCC = 2.7 V to 3.6 V 2 — 4 VCC = 1.8 V to 3.6 V OSC1, OSC2 100 — 500 ns (1000) VCC = 2.7 V to 3.
Section 15 Electrical Characteristics Item Applicable Symbol Pins Oscillation trc stabilization time Values Min OSC1, OSC2 — — X1, X2 External clock high width tCPH OSC1 X1 External clock low width External clock rise time External clock fall time tCPL tCPr tCPf OSC1 Typ Max Unit 4.0 — Crystal Oscillator Parameters Except the above — 50 Except the above — — 2 — 4 — s 40 — — 100 — — — 15.26 or 13.02 — µs ns Test Condition Reference Figure Figure 15.10 VCC = 2.
Section 15 Electrical Characteristics Item Applicable Symbol Pins UD pin minimum tUDH modulation width tUDL UD Values Min Typ Max Unit 4 — — tcyc Test Condition Reference Figure Figure 15.4 tsubcyc Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 2. Figures in parentheses are the maximum tOSC rate with external clock input. Rev. 6.
Section 15 Electrical Characteristics Table 15.20 Serial Interface (SCI1) Timing Item Applicable Symbol Pins Values Min Typ Max Unit Test Condition Reference Figure Input clock cycle tScyc SCK1 4 — — tcyc Figure 15.5 Input clock high width tSCKH SCK1 0.4 — — tScyc Figure 15.5 Input clock low width tSCKL SCK1 0.4 — — tScyc Figure 15.5 Input clock rise time tSCKr SCK1 — — 80.0 ns Figure 15.5 Input clock fall time tSCKf SCK1 — — 80.0 ns Figure 15.
Section 15 Electrical Characteristics Table 15.21 Serial Interface (SCI3-1, SCI3-2) Timing Values Item Symbol Min Typ Max Unit Input clock Asynchronous tScyc 4 — — tcyc or cycle Synchronous 6 — — tsubcyc Reference Test Conditions Figure Figure 15.6 Input clock pulse width tSCKW 0.4 — 0.6 tScyc Figure 15.6 Transmit data delay time (synchronous) tTXD — — 1 tcyc or tsubcyc Figure 15.7 Receive data setup time (synchronous) tRXS 400.0 — — ns Figure 15.
Section 15 Electrical Characteristics 15.6.4 A/D Converter Characteristics Table 15.22 shows the A/D converter characteristics. Table 15.22 A/D Converter Characteristics Item Applicable Symbol Pins Values Min Typ Max Unit 1.8 3.6 V AVCC + 0.3 V — Test Condition Notes *1 Analog power AVCC supply voltage AVCC Analog input voltage AVIN AN0 to AN11 – 0.3 — Analog power AIOPE AVCC — — 1.2 mA supply current AISTOP1 AVCC — 600 — µA *2 Reference value *3 AVCC = 3.
Section 15 Electrical Characteristics 15.6.5 LCD Characteristics Table 15.23 shows the LCD characteristics. Table 15.23 LCD Characteristics Applicable Values Item Pins Min Typ Max Unit Conditions Segment driver VDS drop voltage SEG1 to SEG40 — — 0.6 V Common driver VDC drop voltage COM1 to COM4 — — 0.3 V *1 ID = 2 µA V1 = 2.7 V to 3.6 V *1 ID = 2 µA V1 = 2.7 V to 3.6 V 1.5 3.5 7 MΩ 2.2 — 3.
Section 15 Electrical Characteristics Table 15.24 Segment External Expansion AC Characteristics Applicable Values Item Symbol Pins Min Typ Max Test Reference Unit Conditions Figure Clock high width tCWH CL1, CL2 800.0 — — ns * Figure 15.8 Clock low width tCWL CL2 800.0 — — ns * Figure 15.8 Clock setup time tCSU CL1, CL2 500.0 — — ns * Figure 15.8 Data setup time tSU DO 300.0 — — ns * Figure 15.8 Data retaining time tDH DO 300.0 — — ns * Figure 15.
Section 15 Electrical Characteristics 15.7 Absolute Maximum Ratings of H8/38347 Group and H8/38447 Group Table 15.25 lists the absolute maximum ratings. Table 15.25 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V *1 CVCC –0.3 to +4.3 V Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage Other than ports B, C Vin –0.3 to VCC +0.3 V Ports B, C AVin –0.3 to AVCC +0.
Section 15 Electrical Characteristics 15.8 Electrical Characteristics of H8/38347 Group and H8/38447 Group 15.8.1 Power Supply Voltage and Operating Ranges The power supply voltage and operating ranges (shaded portions) are shown below. 1. Power Supply Voltage and Oscillation Frequency Range • H8/38347 Group 16.0 fosc (MHz) fW (kHz) 38.4 32.768 2.0 2.7 5.5 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode 2.7 5.5 VCC (V) 2.7 5.5 VCC (V) • All operating modes • H8/38447 Group 16.
Section 15 Electrical Characteristics 2. Power Supply Voltage and Operating Frequency Range • H8/38347 Group 8.0 19.2 φ (MHz) 16.384 1.0 (0.5)*1 2.7 5.5 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) φSUB (kHz) 9.6 8.192 4.8 4.096 1000 φ (kHz) 2.7 5.5 VCC (V) • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 15.625 (7.813)*2 2.7 5.5 VCC (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (except A/D converter) • H8/38447 Group 8.
Section 15 Electrical Characteristics 3. Analog Power Supply Voltage and A/D Converter Operating Range • H8/38347 Group φ (kHz) φ (MHz) 8.0 1.0 0.5 1000 500 2.7 2.7 5.5 AVCC (V) 5.5 AVCC (V) • Active (medium-speed) mode • Sleep (medium-speed) mode • Active (high-speed) mode • Sleep (high-speed) mode 5.0 φ (kHz) φ (MHz) • H8/38447 Group 1.0 (0.5) 1000 625 500 2.7 5.5 AVCC (V) • Active (high-speed) mode • Sleep (high-speed) mode Rev. 6.00 Aug 04, 2006 page 516 of 680 REJ09B0145-0600 2.
Section 15 Electrical Characteristics 15.8.2 DC Characteristics Table 15.26 lists the DC characteristics. Table 15.26 DC Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Values Item Symbol Input high VIH voltage Applicable Pins Min RES, WKP0 to WKP7, IRQ0, to IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK1, SCK32, SCK31 Typ Max Unit Test Condition VCC × 0.8 — VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC × 0.9 — VCC + 0.
Section 15 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input low voltage VIL RES, WKP0 to WKP7, IRQ0, to IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK1, SCK32, SCK31 – 0.3 — VCC × 0.2 V VCC = 4.0 V to 5.5 V – 0.3 — VCC × 0.1 RXD32, UD, RXD31, SI1 – 0.3 — VCC × 0.3 – 0.3 — VCC × 0.2 OSC1 – 0.3 — VCC × 0.2 – 0.3 — VCC × 0.1 EXCL – 0.3 — VCC × 0.
Section 15 Electrical Characteristics Values Item Symbol Output low VOL voltage Applicable Pins Min Typ Max Unit Test Condition P10 to P17, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 — — 0.6 V VCC = 4.0 V to 5.5 V — — 0.5 IOL = 0.4 mA P20 to P27, P30 to P37 — — 1.0 VCC = 4.0 V to 5.5 V — — 0.6 VCC = 4.0 V to 5.5 V Notes IOL = 1.6 mA IOL = 10 mA IOL = 1.
Section 15 Electrical Characteristics Values Item Symbol Active IOPE1 mode current consumption Applicable Pins Min Typ Max Unit Test Condition Notes VCC — 0.8 — mA Active (high-speed) mode VCC = 2.7 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. — 1.2 — *2 *3 *4 Approx. max. value = 1.1 × Typ. — 1.0 — — 1.5 — — 2.0 — — 2.4 — — 4.0 7.0 — 4.9 7.0 Rev. 6.
Section 15 Electrical Characteristics Values Item Symbol Active IOPE2 mode current consumption Applicable Pins Min Typ Max Unit Test Condition Notes VCC — 0.4 — mA Active (mediumspeed) mode VCC = 2.7 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ. — 0.7 — *2 *3 *4 Approx. max. value = 1.1 × Typ. — 0.5 — — 1.0 — — 0.8 — — 1.2 — — 1.2 3.0 — 1.7 3.0 Active (mediumspeed) mode VCC = 5 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ.
Section 15 Electrical Characteristics Values Item Symbol Sleep ISLEEP mode current consumption Applicable Pins Min Typ Max Unit Test Condition Notes VCC — 0.5 — mA VCC = 2.7 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. — 0.8 — *2 *3 *4 Approx. max. value = 1.1 × Typ. Subactive ISUB mode current consumption VCC — 0.7 — — 1.2 — — 1.1 — — 1.6 — — 1.9 5.0 — 2.6 5.0 — 12 — — 15 — — 18 50 — 30 50 Rev. 6.
Section 15 Electrical Characteristics Values Item Applicable Pins Min Typ Max Unit Test Condition Notes Subsleep ISUBSP mode current consumption Symbol VCC — 3.8 16 µA VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (φSUB = φW/2) *3 *4 Watch IWATCH mode current consumption VCC — 1.8 — µA VCC = 2.7 V, Ta = 25°C, 32-kHz crystal resonator used, LCD not used Standby ISTBY mode current consumption — VCC 1.8 — — 3.0 6.0 — 0.3 — — — — 0.3 0.4 0.
Section 15 Electrical Characteristics Item Symbol Allowable output low current (per pin) IOL Allowable output low current (total) ∑IOL Allowable output high –IOH current (per pin) Allowable output high ∑–IOH current (total) Applicable Pins Values Min Typ Max Unit Output pins — except ports 2 and 3 — 2.0 mA Ports 2 and 3 — — 10.0 All pins — — 0.5 Output pins — except ports 2 and 3 — 40.0 Ports 2 and 3 — — 80.0 All pins — — 20.0 All output pins — — 2.0 — — 0.
Section 15 Electrical Characteristics 3.
Section 15 Electrical Characteristics 15.8.3 AC Characteristics Table 15.27 lists the control signal timing and table 15.28 and 15.29 list the serial interface timing. Table 15.27 Control Signal Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Item Symbol System clock oscillation frequency fOSC OSC clock (φOSC) cycle time tOSC System clock (φ) cycle time Applicable Pins OSC1, OSC2 OSC1, OSC2 tcyc Values Min Typ Max Unit Test Condition 2.
Section 15 Electrical Characteristics Item Symbol External clock high tCPH width External clock low width External clock rise time External clock fall time tCPL tCPr tCPf Values Applicable Pins Min Typ Max Unit OSC1 25 — — ns 25 — — — Test Condition Reference Figure Figure 15.1*3 VCC = 4.5 to 5.5 V VCC = 2.7 to 5.5 V Figure 15.1*4 40 — EXCL — 15.26 or — 13.02 µs Figure 15.1 OSC1 25 — — ns Figure 15.1*3 25 — — VCC = 4.5 to 5.5 V 40 — — VCC = 2.7 to 5.
Section 15 Electrical Characteristics Item Symbol Input pin low width tIL UD pin minimum transition width tUDH tUDL Applicable Pins Values Min Max Unit 2 IRQ00 to IRQ04, WKP0 to WKP7, ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH — — tcyc tsubcyc Figure 15.3 UD — — tcyc tsubcyc Figure 15.4 4 Test Condition Reference Figure Typ Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2.
Section 15 Electrical Characteristics Table 15.29 Serial Interface (SCI3) Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Values Item Symbol Min Typ Max Unit Input clock Asynchronous cycle Clocked synchronous tscyc 4 — — 6 — Input clock pulse width tSCKW 0.
Section 15 Electrical Characteristics 15.8.4 A/D Converter Characteristics Table 15.30 shows the A/D converter characteristics. Table 15.30 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Values Applicable Pins Min Typ Max Unit Analog power supply AVCC voltage AVCC 2.7 — 5.5 V Analog input voltage AN0 to AN11 – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AISTOP1 AVCC — — 1.
Section 15 Electrical Characteristics 15.8.5 LCD Characteristics Table 15.31 shows the LCD characteristics. Table 15.31 LCD Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Item Symbol Segment driver step-down voltage VDS Common driver step-down voltage VDC LCD power supply split-resistance RLCD Liquid crystal display voltage VLCD Applicable Pins Values Reference Figure Min Typ Max Unit Test Condition SEG1 to SEG40 — — 0.
Section 15 Electrical Characteristics 15.8.6 Flash Memory Characteristics Table 15.32 Flash Memory Characteristics Condition: AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of operating voltage when reading), VCC = 3.0 V to 5.
Section 15 Electrical Characteristics Values Item Erase Symbol Min Typ Max Unit Wait time after SWE-bit setting*1 x 1 — — µs Wait time after ESU-bit setting*1 y 100 — — µs Wait time after E-bit setting*1*6 z 10 — 100 ms Wait time after E-bit clear*1 α 10 — — µs Wait time after ESU-bit clear*1 β 10 — — µs Wait time after EV-bit setting*1 γ 20 — — µs Wait time after dummy write*1 ε 2 — — µs Wait time after EV-bit clear*1 η 4 — — µs Wait time after SWE-bit
Section 15 Electrical Characteristics 10. This is a data retain characteristic when reprogramming is performed within the specification range including this minimum value. Rev. 6.
Section 15 Electrical Characteristics 15.9 Operation Timing Figures 15.1 to 15.8 show timing diagrams. t OSC , tw OSC1 x1 EXCL VIH VIL t CPH t CPL t CPr t CPf Figure 15.1 Clock Input Timing RES VIL tREL Figure 15.2 RES Low Width IRQ0 to IRQ4, WKP0 to WKP7, ADTRG, TMIC, TMIF, TMIG, AEVL, AEVH VIH VIL t IL t IH Figure 15.3 Input Timing Rev. 6.
Section 15 Electrical Characteristics VIH UD VIL t UDL t UDH Figure 15.4 UD Pin Minimum Modulation Width Timing tscyc SCK1 VIH or VOH* VIL or VOL* tSCKL tSCKH tSCKf tSCKr tSOD VOH* VOL* SO1 tSIS tSIH SI1 Note: * Output timing reference levels Output high level VOH = 1/2 VCC + 0.2 V Output low level VOL = 0.8 V See figure 15.9 for the load conditions. Figure 15.5 SCI1 Input/Output Timing Rev. 6.
Section 15 Electrical Characteristics t SCKW SCK 31 SCK 32 t scyc Figure 15.6 SCK3 Input Clock Timing t scyc SCK 31 VIH or VOH * SCK 32 VIL or VOL * t TXD TXD31 TXD32 (transmit data) * VOH VOL * t RXS t RXH RXD31 RXD32 (receive data) Note: * Output timing reference levels Output high VOH = 1/2 VCC + 0.2 V Output low VOL = 0.8 V Load conditions are shown in figure 15.9. Figure 15.7 SCI3 Synchronous Mode Input/Output Timing Rev. 6.
Section 15 Electrical Characteristics tCT VCC − 0.5 V CL1 0.4 V tCWH tCWH tCSU VCC − 0.5 V CL2 0.4 V tCSU tCWL tCT VCC − 0.5 V 0.4 V DO tSU M tDH 0.4 V tDM Figure 15.8 Segment Expansion Signal Timing Rev. 6.
Section 15 Electrical Characteristics 15.10 Output Load Circuit VCC 2.4 kΩ Output pin 30 pF 12 k Ω Figure 15.9 Output Load Condition Rev. 6.
Section 15 Electrical Characteristics 15.11 Resonator LS CS RS OSC1 OSC2 CO Ceramic Oscillator Parameters Manufacturer Products Name Frequency 4 MHz RS Manufacturer's Publicly Released Values MURATA CSTLS Max. 8.8 ½ 4M00G 53/56 CO Max. 36 pF Crystal Oscillator Parameters Manufacturer Products Name Frequency 4.193 MHz RS Manufacturer's Publicly Released Values Nihon Denpa NR-18 Max. 100 ½ Kogyo Max. 16 pF CO Figure 15.
Section 15 Electrical Characteristics 15.12 Usage Note Each of the products covered in this manual satisfy the electrical characteristics indicated. However, the actual electrical characteristics, operating margin and noise margin may differ from the indicated values due to differences in the manufacturing process, built-in ROM, layout pattern and other factors.
Section 15 Electrical Characteristics Rev. 6.
Appendix A CPU Instruction Set Appendix A CPU Instruction Set A.
Appendix A CPU Instruction Set Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set 4 2 — — — — 4 — — 2 — — W #xx:16 → Rd MOV.W Rs, Rd W Rs16 → Rd16 MOV.W @Rs, Rd W @Rs16 → Rd16 MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16 MOV.W @Rs+, Rd W @Rs16 → Rd16 Rs16+2 → Rs16 MOV.W @aa:16, Rd W @aa:16 → Rd16 MOV.W Rs, @Rd W Rs16 → @Rd16 MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16) MOV.W Rs, @–Rd W Rd16–2 → Rd16 Rs16 → @Rd16 MOV.
Appendix A CPU Instruction Set W Rd16+Rs16 → Rd16 2 — (1) ADDX.B #xx:8, Rd B Rd8+#xx:8 +C → Rd8 ↔ ↔ ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ 2 ↔ ↔ — H N Z (2) V C No. of States ADD.W Rs, Rd @(d:8, PC) @@aa Implied — 2 @Rn @(d:16, Rn) @–Rn/@Rn+ @aa: 8/16 2 #xx: 8/16 B Rd8+Rs8 → Rd8 Rn B Rd8+#xx:8 → Rd8 ADD.B Rs, Rd I ↔ ↔ ↔ ↔ ↔ ADD.B #xx:8, Rd Operation ↔ ↔ ↔ ↔ ↔ Mnemonic Operand Size Addressing Mode/ Instruction Length (bytes) Condition Code 2 2 2 2 — 2 — — — — — — 2 ADDS.
Appendix A CPU Instruction Set 0 Implied @@aa @aa: 8/16 @(d:8, PC) @(d:16, Rn) @–Rn/@Rn+ @Rn #xx: 8/16 Rn No.
Appendix A CPU Instruction Set BCLR Rn, @Rd B (Rn8 of @Rd16) ← 0 BCLR Rn, @aa:8 B (Rn8 of @aa:8) ← 0 BNOT #xx:3, Rd B (#xx:3 of Rd8) ← (#xx:3 of Rd8) BNOT #xx:3, @Rd B (#xx:3 of @Rd16) ← (#xx:3 of @Rd16) BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ← (#xx:3 of @aa:8) BNOT Rn, Rd B (Rn8 of Rd8) ← (Rn8 of Rd8) BNOT Rn, @Rd B (Rn8 of @Rd16) ← (Rn8 of @Rd16) BNOT Rn, @aa:8 B (Rn8 of @aa:8) ← (Rn8 of @aa:8) B (#xx:3 of Rd8) → Z BTST #xx:3, @Rd B (#xx:3 of @Rd16) → Z BTST #xx:3, @aa:8 B (#xx:3 of @aa:
Appendix A CPU Instruction Set B C∧(#xx:3 of Rd8) → C BIAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) → C BIAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) → C BOR #xx:3, Rd B C∨(#xx:3 of Rd8) → C BOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) → C BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C BIOR #xx:3, Rd B C∨(#xx:3 of Rd8) → C BIOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) → C BIOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C BXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) → C BXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) → C BXOR #xx:3, @aa:8 B C⊕(#xx:3
Appendix A CPU Instruction Set JMP @Rn — PC ← Rn16 JMP @aa:16 — PC ← aa:16 JMP @@aa:8 — PC ← @aa:8 BSR d:8 — SP–2 → SP PC → @SP PC ← PC+d:8 JSR @Rn — SP–2 → SP PC → @SP PC ← Rn16 JSR @aa:16 — SP–2 → SP PC → @SP PC ← aa:16 JSR @@aa:8 2 H N Z V C — — — — — — 4 4 — — — — — — 6 2 — — — — — — 8 2 — — — — — — 6 2 — — — — — — 6 4 SP–2 → SP PC → @SP PC ← @aa:8 I No.
Appendix A CPU Instruction Set (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 in the H8/3847R Group and 4n + 8 in the H8/3847S Group, H8/38347 Group and H8/38447 Group (n = value of R4L). (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0. Rev. 6.
Appendix A CPU Instruction Set A.2 Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. Rev. 6.
Rev. 6.00 Aug 04, 2006 page 552 of 680 REJ09B0145-0600 XOR AND MOV D E F Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
Appendix A CPU Instruction Set A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction.
Appendix A CPU Instruction Set Table A.3 Number of Cycles in Each Instruction Execution Status Access Location (instruction cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM — Internal operation SN Note: * 1 Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access for details. Rev. 6.
Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Fetch I Instruction Mnemonic ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W Rs, Rd 1 ADDS.W #1, Rd 1 ADDS.W #2, Rd 1 ADDX.B #xx:8, Rd 1 ADDX.B Rs, Rd 1 ADDS ADDX AND ANDC BAND Bcc BCLR AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 ANDC #xx:8, CCR 1 Branch Stack Byte Data Word Data Internal Addr.
Appendix A CPU Instruction Set Instruction Mnemonic Instruction Fetch I BIAND BIAND #xx:3, Rd 1 BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST Branch Stack Byte Data Word Data Internal Addr.
Appendix A CPU Instruction Set Instruction BTST Mnemonic Instruction Fetch I Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N BTST #xx:3, Rd 1 BTST #xx:3, @Rd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @Rd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @Rd 2 1 BXOR #xx:3, @aa:8 2 1 CMP. B #xx:8, Rd 1 CMP. B Rs, Rd 1 CMP.W Rs, Rd 1 DAA DAA.B Rd 1 DAS DAS.B Rd 1 DEC DEC.B Rd 1 DIVXU DIVXU.
Appendix A CPU Instruction Set Instruction MOV Mnemonic Instruction Fetch I Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N MOV.B Rs, @(d:16, Rd) 2 1 MOV.B Rs, @–Rd 1 1 MOV.B Rs, @aa:8 1 1 MOV.B Rs, @aa:16 2 1 MOV.W #xx:16, Rd 2 2 MOV.W Rs, Rd 1 MOV.W @Rs, Rd 1 1 MOV.W @(d:16, Rs), Rd 2 1 MOV.W @Rs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W Rs, @Rd 1 1 MOV.W Rs, @(d:16, Rd) 2 1 MOV.W Rs, @–Rd 1 1 1 MOV.
Appendix A CPU Instruction Set Instruction Mnemonic Instruction Fetch I SUB SUB.B Rs, Rd 1 SUB.W Rs, Rd 1 SUBS SUBS.W #1, Rd 1 SUBS.W #2, Rd 1 Branch Stack Byte Data Word Data Internal Addr. Read Operation Access Access Operation J K L M N POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX.B #xx:8, Rd 1 XOR XORC SUBX.B Rs, Rd 1 XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XORC #xx:8, CCR 1 Notes: 1. n: Initial value in R4L.
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 Addresses Upper Address: H'F0 Lower Address Register Name H'20 Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name FLMCR1 — SWE ESU PSU EV PV E P ROM H'21 FLMCR2 FLER — — — — — — — H'22 FLPWCR PDWND — — — — — — — H'23 EBR EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FENR FLSHE — — — — — — — H'24 H'25 H'26 H'27 H'28 H'29 H'2A H'2B H'2C H'2D H'2E H'2F Rev. 6.
Appendix B Internal I/O Registers Upper Address: H'FF Lower Register Bit Names Address Name Bit 7 Module H'90 WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System control Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name H'91 SPCR — — SPC32 SPC31 SCINV3 SCINV2 SCINV1 SCINV0 SCI H'92 CWOSR — — — — — — — CWOS Timer A H'95 ECCSR OVH OVL — CH2 CUEH CUEL CRCH CRCL H'96 ECH ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 H'97 ECL ECL7 ECL6 ECL5
Appendix B Internal I/O Registers Lower Register Bit Names Address Name Bit 7 Module H'B2 TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON H'B3 TCW TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 H'B4 TMC TMC7 TMC6 TMC5 — — TMC2 H'B5 TCC/ TLC TCC/ TLC7 TCC6/ TLC6 TCC5/ TLC5 TCC4/ TLC4 TCC3/ TLC3 TCC2/ TLC2 H'B6 TCRF TOLH CKSH2 CKSH1 CKSH0 TOLL H'B7 TCSRF OVFH CMFH OVIEH CCLRH H'B8 TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFL6 TCFL5 TCFL4 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 N
Appendix B Internal I/O Registers Lower Register Bit Names Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Module H'D9 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 I/O Port H'DA PDR7 P77 P76 P75 P74 P73 P72 P71 P70 H'DB PDR8 P87 P86 P85 P84 P83 P82 P81 P80 H'DC PDR9 P97 P96 P95 P94 P93 P92 P91 P90 H'DD PDRA — — — — PA3 PA2 PA1 PA0 H'DE PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 H'DF PDRC — — — — PC3 PC2 PC1 PC0 H'E0 P
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 Bit H'F020 Flash Memory 7 6 5 4 3 2 1 0 SWE ESU PSU EV PV E P Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W Program 0 Program mode cleared (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 and PSU = 1 Erase 0 Erase mode cleared (initial value) 1 Transition to erase mode [Setting condition] When SWE = 1 and ESU = 1 Program-Verify 0 Prog
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 Bit H'F021 Flash Memory 7 6 5 4 3 2 1 0 FLER Initial value 0 0 0 0 0 0 0 0 Read/Write R Flash memory error Note: A write to FLMCR2 is prohibited.
Appendix B Internal I/O Registers EBR—Erase Block Register Bit H'F023 Flash Memory 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Blocks 7 to 0 0 When a block of EB7 to EB0 is not selected (initial value) 1 When a block of EB7 to EB0 is selected Note: Set the bit of EBR to H'00 when erasing.
Appendix B Internal I/O Registers WEGR—Wakeup Edge Select Register Bit 7 6 H'90 5 4 3 2 System control 1 0 WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W WKPn edge selected 0 1 WKPn pin falling edge detected WKPn pin rising edge detected (n = 0 to 7) Rev. 6.
Appendix B Internal I/O Registers SPCR—Serial Port Control Register Bit H'91 7 6 5 4 3 2 SCI 1 0 — — SPC32 SPC31 Initial value 1 1 0 0 SCINV3 SCINV2 SCINV1 SCINV0 0 0 0 0 Read/Write — — R/W R/W R/W R/W R/W R/W RXD31 pin input data inversion switch 0 1 RXD31 input data is not inverted RXD31 input data is inverted TXD31 pin output data inversion switch 0 1 TXD31 output data is not inverted TXD31 output data is inverted RXD32 pin input data inversion switch 0 1 RXD32 input
Appendix B Internal I/O Registers CWOSR—Subclock Output Select Register Bit H'92 Timer A 7 6 5 4 3 2 1 0 — — — — — — — CWOS Initial value 1 1 1 1 1 1 1 0 Read/Write R R R R R R R R/W TMOW pin clock select 0 1 Rev. 6.
Appendix B Internal I/O Registers ECCSR—Event Counter Control/Status Register Bit H'95 AEC 7 6 5 4 3 2 1 0 CRCL OVH OVL CH2 CUEH CUEL CRCH Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/W R/W R/W R/W R/W R/W Counter reset control L 0 ECL is reset 1 ECL reset is cleared and count-up function is enabled Counter reset control H 0 ECH is reset 1 ECH reset is cleared and count-up function is enabled Count-up enable L 0 ECL event clock input is disabled.
Appendix B Internal I/O Registers ECH—Event Counter H Bit H'96 AEC 7 6 5 4 3 2 1 0 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Note: * ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit event counter (EC).
Appendix B Internal I/O Registers SMR31—Serial Mode Register 31 Bit H'98 SCI31 7 6 5 4 3 2 COM31 CHR31 PE31 PM31 STOP31 MP31 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 1 0 CKS311 CKS310 Clock select 0 0 φ clock 0 1 φw/2 clock 1 0 φ/16 clock 1 1 φ/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 O
Appendix B Internal I/O Registers BRR31—Bit Rate Register 31 Bit 7 6 H'99 5 4 3 2 SCI31 1 0 BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Serial transmit/receive bit rate Rev. 6.
Appendix B Internal I/O Registers SCR31—Serial Control Register 31 Bit H'9A 3 SCI31 7 6 5 4 TIE31 RIE31 TE31 RE31 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 MPIE31 TEIE31 CKE311 CKE310 Clock enable Bit 0 Bit 1 CKE311 CKE310 0 0 0 1 1 0 1 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial c
Appendix B Internal I/O Registers TDR31—Transmit Data Register 31 Bit 7 6 H'9B 5 4 3 2 SCI31 1 0 TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for transfer to TSR Rev. 6.
Appendix B Internal I/O Registers SSR31—Serial Status Register31 Bit 7 H'9C 6 4 5 TDRE31 RDRF31 OER31 Initial value 1 0 * Read/Write R/(W) 0 0 * * R/(W) 3 FER31 R/(W) 2 R/(W) 0 1 PER31 TEND31 MPBR31 MPBT31 0 * SCI3 * R/(W) 1 0 0 R R R/W Multiprocessor bit transfer 0 A 0 multiprocessor bit is transmitted 1 A 1 multiprocessor bit is transmitted Multiprocessor bit receive 0 Data in which the multiprocessor bit is 0 has been received 1 Data in which the multiprocessor bi
Appendix B Internal I/O Registers RDR31—Receive Data Register 31 Bit 7 6 H'9D 5 4 3 2 SCI31 1 0 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Serial receiving data are stored Rev. 6.
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit H'A0 SCI1 7 6 5 4 3 2 1 0 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock select 2 to 0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 Prescaler Division Ratio φ/1024 φ/256 φ/64 φ/32 φ/16 φ/8 φ/4 φW/4 Serial Clock Cycle Clock Cycle φ = 2.5 MHz 409.6 µs 102.4 µs 25.6 µs 12.8 µs 6.4 µs 3.2 µs 1.
Appendix B Internal I/O Registers SCSR1—Serial Control Status Register 1 Bit H'A1 SCI1 7 6 5 4 3 2 1 0 SOL ORER MTRF STF Initial value 1 0 0 1 1 1 0 0 Read/Write R/W R/(W)* R R/W Start flag 0 Read Write 1 Read Write Transfer operation stopped Invalid Transfer operation in progress Starts transfer operation Tail mark transmission flag 0 Idle state, or 8-bit/16-bit data transfer in progress 1 Tail mark transmission in progress Overrun error flag 0 [Clear
Appendix B Internal I/O Registers SDRU—Serial Data Register U Bit Initial value Read/Write H'A2 SCI1 7 6 5 4 3 2 1 0 SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W Used for transmit data setting and receive data storage 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data register SDRL—Serial Data Register L Bit Initial value Read/Write H'A3 SCI1
Appendix B Internal I/O Registers SMR32—Serial Mode Register 32 Bit H'A8 SCI32 7 6 5 4 3 2 COM32 CHR32 PE32 PM32 STOP32 MP32 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 1 0 CKS321 CKS320 Clock select 0 0 φ clock 0 1 φw/2 clock 1 0 φ/16 clock 1 1 φ/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 O
Appendix B Internal I/O Registers BRR32—Bit Rate Register 32 Bit 7 6 H'A9 5 4 3 2 SCI32 1 0 BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Serial transmit/receive bit rate Rev. 6.
Appendix B Internal I/O Registers SCR32—Serial Control Register 32 Bit H'AA 3 SCI32 7 6 5 4 TIE32 RIE32 TE32 RE32 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 2 1 Clock enable Bit 0 Bit 1 CKE321 CKE320 0 0 0 1 1 0 1 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial clock output Internal clock Clock
Appendix B Internal I/O Registers TDR32—Transmit Data Register 32 Bit 7 6 H'AB 5 4 3 2 SCI32 1 0 TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for transfer to TSR Rev. 6.
Appendix B Internal I/O Registers SSR32—Serial Status Register 32 Bit 7 H'AC 6 4 5 TDRE32 RDRF32 OER32 Initial value 1 0 * Read/Write R/(W) 0 0 * * R/(W) 3 FER32 R/(W) 2 R/(W) 0 1 PER32 TEND32 MPBR32 MPBT32 0 * SCI32 * R/(W) 1 0 0 R R R/W Multiprocessor bit transfer 0 A 0 multiprocessor bit is transmitted 1 A 1 multiprocessor bit is transmitted Multiprocessor bit receive 0 Data in which the multiprocessor bit is 0 has been received 1 Data in which the multiprocessor
Appendix B Internal I/O Registers RDR32—Receive Data Register 32 Bit 7 6 H'AD 5 4 3 2 SCI32 1 0 RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Serial receiving data are stored Rev. 6.
Appendix B Internal I/O Registers TMA—Timer Mode Register A Bit H'B0 Timer A 7 6 5 4 3 2 1 0 TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/W R/W R/W — R/W R/W R/W R/W Clock output select* Internal clock select 0 0 0 φ/32 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 1 φ/16 0 0 0 0 PSS φ/8192 0 1 0 φ/8 0 0 1 0 PSS φ/4096 0 1 1 φ/4 0 0 PSS 1 0 φ/2048 1 0 0 φ W/32 0 0 PSS 1 1 φ/512 1 0 1 φ W/16 1 0 0 PSS 0 φ/256 1
Appendix B Internal I/O Registers TCA—Timer Counter A Bit H'B1 Timer A 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Rev. 6.
Appendix B Internal I/O Registers TCSRW—Timer Control/Status Register W Bit Initial value Read/Write H'B2 Watchdog timer 7 6 5 4 3 2 1 0 B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST 1 0 1 0 1 0 1 0 R R/(W)* R R/(W)* R R/(W) * R R/(W) * Watchdog timer reset 0 [Clearing conditions] • Reset by RES pin • When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit 0 Bit 0 is write-enabled 1 B
Appendix B Internal I/O Registers TCW—Timer Counter W Bit H'B3 Watchdog timer 7 6 5 4 3 2 1 0 TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value TMC—Timer Mode Register C Bit H'B4 Timer C 7 6 5 4 3 2 1 0 TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W Clock select 0 0 0 Internal clock: φ/8192 0 0 1 Interna
Appendix B Internal I/O Registers TCC—Timer Counter C Bit H'B5 Timer C 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Note: TCC is assigned to the same address as TLC. In a read, the TCC value is read.
Appendix B Internal I/O Registers TCRF—Timer Control Register F Bit H'B6 Timer F 7 6 5 4 3 2 1 0 TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Clock select L 0 * * 1 1 1 0 0 1 0 1 0 1 1 1 Counting on external event (TMIF) rising/falling edge Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φw/4 Toggle output level L 0 1 Low level High level Clock select H 0 * * 1 1 0 0 0 1
Appendix B Internal I/O Registers TCSRF—Timer Control/Status Register F Bit H'B7 Timer F 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/W R/W R/(W)* R/(W)* R/W R/W Counter clear L 0 TCFL clearing by compare match is disabled 1 TCFL clearing by compare match is enabled Timer overflow interrupt enable L 0 TCFL overflow interrupt request is disabled 1 TCFL overflow interrupt request is enabled Co
Appendix B Internal I/O Registers TCFH—8-Bit Timer Counter FH Bit H'B8 Timer F 7 6 5 4 3 2 1 0 TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF).
Appendix B Internal I/O Registers OCRFL—Output Compare Register FL Bit 7 6 5 H'BB 4 3 2 Timer F 1 0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). Rev. 6.
Appendix B Internal I/O Registers TMG—Timer Mode Register G Bit H'BC Timer G 7 6 5 4 3 2 1 0 OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* W W W W W W Clock select 0 0 Internal clock: counting on φ/64 0 1 Internal clock: counting on φ/32 1 0 Internal clock: counting on φ/2 1 1 Internal clock: counting on φw/4 Counter clear 0 0 TCG clearing is disabled 0 1 TCG cleared by falling edge of input capture input signal 1 0 T
Appendix B Internal I/O Registers ICRGF—Input Capture Register GF Bit 7 6 H'BD 5 4 3 2 Timer G 1 0 ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR Bit 7 6 H'BE 5 4 3 2 Timer G 1 0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores TC
Appendix B Internal I/O Registers LPCR—LCD Port Control Register Bit H'C0 LCD controller/driver 7 6 5 4 3 2 1 0 DTS1 DTS0 CMX SGX SGS3 SGS2 SGS1 SGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Segment driver select Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Function of Pins SEG32 to SEG1 SEG32 SEG24 SEG16 SEG8 SEG40 SGX SGS3 SGS2 SGS1 SGS0 to SEG33 to SEG25 to SEG17 to SEG9 to SEG1 0 0 0 0 0 Port Port Port Port Port 1 0 0 0 0 SEG Port Port Port Port 1
Appendix B Internal I/O Registers LCR—LCD Control Register Bit H'C1 LCD controller/driver 7 6 5 4 3 2 1 0 PSW ACT DISP CKS3 CKS2 CKS1 CKS0 Initial value 1 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W Frame frequency select Bit 3 Bit 2 Bit 1 Bit 1 CKS3 CKS2 CKS1 CKS0 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 Display data control 0 Blank data is displayed 1 LCD RAM data is displayed Display function activate 0 LCD controller/driver o
Appendix B Internal I/O Registers LCR2—LCD Control Register 2 Bit H'C2 LCD 7 6 5 4 3 2 1 0 LCDAB Ñ Ñ Ñ CDS3 CDS2 CDS1 CDS0 Initial value 0 1 1 0 0 0 0 0 Read/Write R/W Ñ Ñ R/W R/W R/W R/W R/W Charge/discharge pulse duty cycle select Bit 3 Bit 2 Bit 1 Bit 0 Duty Cycle CDS3 CDS2 CDS1 CDS0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 * * 0 1 0 1 0 1 0 1 * * 1 1/8 2/8 3/8 4/8 5/8 6/8 0 1/16 1/32 * Don't care A waveform/B waveform switching control 0 Drive us
Appendix B Internal I/O Registers ADRRH—A/D Result Register H ADRRL—A/D Result Register L H'C4 H'C5 A/D converter ADRRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R A/D conversion result ADRRL Bit Initial value Read/Write 7 6 5 4 3 2 1 0 ADR1 ADR0 — — — — — — — — — — — — — — — — — — Undefined Undefined R R A/D conv
Appendix B Internal I/O Registers AMR—A/D Mode Register Bit H'C6 A/D converter 7 6 5 4 3 2 1 0 CKS TRGE CH3 CH2 CH1 CH0 Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 0 0 1 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AN 8 AN 9 AN 10 AN 11 * Don't care Ext
Appendix B Internal I/O Registers ADSR—A/D Start Register Bit H'C7 A/D converter 7 6 5 4 3 2 1 0 ADSF — — — — — — — Initial value 0 1 1 1 1 1 1 1 Read/Write R/W — — — — — — — A/D status flag 0 Read Indicates completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion Rev. 6.
Appendix B Internal I/O Registers PMR1—Port Mode Register 1 Bit H'C8 7 6 5 4 3 2 1 0 IRQ3 IRQ2 IRQ1 IRQ4 TMIG TMOFH TMOFL TMOW Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I/O port P10/TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P11/TMOFL pin function switch 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin P12/TMOFH pin function switch 0 Functions as P12 I/O pin 1 Functions as TMOFH output pin
Appendix B Internal I/O Registers PMR2—Port Mode Register 2 H'C9 I/O port • H8/3847R Group and H8/3847S Group Bit 7 6 5 4 3 2 1 0 — — POF1 — — SO1 SI1 SCK1 Initial value 1 1 0 1 1 0 0 0 Read/Write — — R/W — — R/W R/W R/W P20/SCK1 pin function switch 0 Functions as P20 I/O pin 1 Functions as SCK1 I/O pin P21/SI1 pin function switch 0 Functions as P21 I/O pin 1 Functions as SI1 input pin P22/SO1 pin function switch 0 Functions as P22 I/O pin 1 Functions as SO1 output pin
Appendix B Internal I/O Registers • H8/38347 Group and H8/38447 Group Bit 7 6 5 4 3 2 1 0 EXCL — POF1 — — SO1 SI1 SCK1 Initial value 0 1 0 1 1 0 0 0 Read/Write R/W — R/W — — R/W R/W R/W P20/SCK1 pin function switch 0 Functions as P20 I/O pin 1 Functions as SCK1 I/O pin P21/SI1 pin function switch 0 Functions as P21 I/O pin 1 Functions as SI1 input pin P22/SO1 pin function switch 0 Functions as P22 I/O pin 1 Functions as SO1 output pin P22/SO1 pin PMOS control 0 CMOS outpu
Appendix B Internal I/O Registers PMR3—Port Mode Register 3 Bit H'CA 7 6 5 4 3 2 1 0 AEVL AEVH WDCKS NCS IRQ0 RESO* UD PWM Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W I/O port P30/PWM pin function switch 0 Functions as P30 I/O pin 1 Functions as PWM output pin P31/UD pin function switch 0 Functions as P31 I/O pin 1 Functions as UD input pin P32/RESO pin function switch 0 Functions as P32 I/O pin 1 Functions as RESO I/O pin P43/IRQ0 pin funct
Appendix B Internal I/O Registers PMR4—Port Mode Register 4 Bit 7 6 H'CB 5 4 3 I/O port 2 1 0 NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 0 P2n is CMOS output 1 P2n is NMOS open-drain output (n = 7 to 0) PMR5—Port Mode Register 5 Bit H'CC I/O port 7 6 5 4 3 2 1 0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R
Appendix B Internal I/O Registers PWCR—PWM Control Register Bit H'D0 7 6 5 4 3 2 14-bit PWM 1 0 Initial value 1 1 1 1 1 1 0 0 Read/Write W W PWCR1 PWCR0 Clock select 0 The input clock is φ/2 (tφ* = 2/φ) The conversion period is 16,384/φ, with a minimum modulation width of 1/φ The input clock is φ/4 (tφ* = 4/φ) The conversion period is 32,768/φ, with a minimum modulation width of 2/φ 1 The input clock is φ/8 (tφ* = 8/φ) The conversion period is 65,5
Appendix B Internal I/O Registers PDR1—Port Data Register 1 Bit H'D4 I/O ports 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P1 3 P1 2 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 1 pins PDR2—Port Data Register 2 Bit H'D5 I/O ports 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 2 pins PDR3—Port Data Register 3
Appendix B Internal I/O Registers PDR5—Port Data Register 5 Bit H'D8 I/O ports 7 6 5 4 3 2 1 0 P5 7 P56 P55 P54 P53 P52 P51 P50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 5 pins PDR6—Port Data Register 6 Bit H'D9 I/O ports 7 6 5 4 3 2 1 0 P6 7 P66 P65 P64 P63 P62 P61 P60 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 6 pins PDR7—Port Data Register 7
Appendix B Internal I/O Registers PDR9—Port Data Register 9 Bit H'DC I/O ports 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 9 pins PDRA—Port Data Register A Bit H'DD I/O ports 7 6 5 4 3 2 1 0 PA3 PA2 PA1 PA0 Initial value 1 1 1 1 0 0 0 0 Read/Write R/W R/W R/W R/W Data for port A pins PDRB—Port Data Register B Bit Read/Write
Appendix B Internal I/O Registers PUCR1—Port Pull-Up Control Register 1 Bit 7 6 5 H'E0 4 3 2 I/O ports 0 1 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 1 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR1 specification is 0.
Appendix B Internal I/O Registers PUCR5—Port Pull-Up Control Register 5 Bit 7 6 5 H'E2 4 3 2 I/O ports 0 1 PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 5 input pull-up MOS control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR5 specification is 0.
Appendix B Internal I/O Registers PCR1—Port Control Register 1 Bit H'E4 I/O ports 7 6 5 4 3 2 1 0 PCR17 PCR16 PCR15 PCR14 PCR13 PCR1 2 PCR11 PCR10 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 1 input/output select 0 Input pin 1 Output pin PCR2—Port Control Register 2 Bit H'E5 I/O ports 7 6 5 4 3 2 1 0 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 2 inpu
Appendix B Internal I/O Registers PCR4—Port Control Register 4 Bit H'E7 I/O ports 7 6 5 4 3 2 1 0 — — — — — PCR42 PCR41 PCR40 Initial value 1 1 1 1 1 0 0 0 Read/Write — — — — — W W W Port 4 input/output select 0 Input pin 1 Output pin PCR5—Port Control Register 5 Bit H'E8 I/O ports 7 6 5 4 3 2 1 0 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 5 input/output select 0 Inp
Appendix B Internal I/O Registers PCR7—Port Control Register 7 Bit H'EA I/O ports 7 6 5 4 3 2 1 0 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 7 input/output select 0 Input pin 1 Output pin PCR8—Port Control Register 8 Bit H'EB I/O ports 7 6 5 4 3 2 1 0 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 8 input
Appendix B Internal I/O Registers PCRA—Port Control Register A Bit H'ED I/O ports 7 6 5 4 3 2 — — — — PCRA 3 PCRA 2 Initial value 0 0 0 0 0 0 0 0 Read/Write — — — — W W W W 1 0 PCRA 1 PCRA 0 Port A input/output select 0 Input pin 1 Output pin Rev. 6.
Appendix B Internal I/O Registers SYSCR1—System Control Register 1 Bit H'F0 System control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 LSON MA1 MA0 Initial value 0 0 0 0 0 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W Active (medium-speed) mode clock select 0 0 φ osc /16 1 φ osc /32 1 0 φ osc /64 1 φ osc/128 Low speed on flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ SUB) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 Bit H'F1 System control 7 6 5 4 3 2 1 0 NESEL DTON MSON SA1 SA0 Initial value 1 1 1 1 0 0 0 0 Read/Write R/W R/W R/W R/W R/W Subactive mode clock select Medium speed on flag 0 0 φ W/8 1 φ W/4 1 * φ W/2 *: Don't care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag 0 • When a SLEEP instruction is executed in active mode, a transition is
Appendix B Internal I/O Registers IEGR—IRQ Edge Select Register Bit H'F2 System control 7 6 5 4 3 2 1 0 IEG4 IEG3 IEG2 IEG1 IEG0 Initial value 0 1 1 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W IRQ0 edge select 0 Falling edge of IRQ0 pin input is detected 1 Rising edge of IRQ0 pin input is detected IRQ1 edge select 0 Falling edge of IRQ1, TMIC pin input is detected 1 Rising edge of IRQ1, TMIC pin input is detected IRQ2 edge select 0 Falling edge of IRQ2 pin inpu
Appendix B Internal I/O Registers IENR1—Interrupt Enable Register 1 Bit H'F3 System control 7 6 5 4 3 2 1 0 IENTA IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IRQ4 to IRQ0 interrupt enable 0 Disables IRQ4 to IRQ0 interrupt requests 1 Enables IRQ4 to IRQ0 interrupt requests Wakeup interrupt enable 0 Disables WKP7 to WKP0 interrupt requests 1 Enables WKP7 to WKP0 interrupt requests SCI1 interrupt enable 0 Di
Appendix B Internal I/O Registers IENR2—Interrupt Enable Register 2 Bit 7 6 5 4 IENDT IENAD — IENTG H'F4 3 2 IENTFH IENTFL 1 0 IENTC IENEC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W System control Asynchronous event counter interrupt enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C interrupt enable 0 Disables timer C interrupt requests 1 Enables timer C interrupt r
Appendix B Internal I/O Registers IRR1—Interrupt Request Register 1 Bit H'F6 System control 7 6 5 4 3 2 1 0 IRRTA IRRS1 IRRI4 IRRI3 IRRI2 IRRI1 IRRI0 Initial value 0 0 1 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRQ4 to IRQ0 interrupt request flags 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 to 0) SCI1
Appendix B Internal I/O Registers IRR2—Interrupt Request Register 2 Bit H'F7 7 6 5 4 IRRDT IRRAD — IRRTG 3 1 0 IRRTC IRREC 2 IRRTFH IRRTFL Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* System control Asynchronous event counter interrupt request flag 0 [Clearing condition] When IRREC = 1, it is cleared by writing 0 1 [Setting condition] When the asynchronous event counter value overflows Timer C interrupt request flag 0 [Cle
Appendix B Internal I/O Registers WPR—Wakeup Interrupt Request Register Bit H'F9 System control 7 6 5 4 3 2 1 0 IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Wakeup interrupt request register 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0 1 [Setting condition] When pin WKPn is designated for wakeup input and a falling edge is input at that pin (n = 7 to
Appendix B Internal I/O Registers CKSTPR1—Clock Stop Register 1 Bit 7 6 H'FA 4 5 3 2 System control 1 0 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Timer A module standby mode control 0 Timer A is set to module standby mode 1 Timer A module standby mode is cleared Timer C module standby mode control 0 Timer C is set to module standby mode 1 Timer C module standby mode is cleared Timer
Appendix B Internal I/O Registers CKSTPR2—Clock Stop Register 2 Bit H'FB 7 6 5 4 3 System control 2 1 0 — — — — Initial value 1 1 1 1 1 1 1 1 Read/Write — — — — R/W R/W R/W R/W AECKSTP WDCKSTP PWCKSTP LDCKSTP LCD module standby mode control 0 LCD is set to module standby mode 1 LCD module standby mode is cleared PWM module standby mode control 0 PWM is set to module standby mode 1 PWM module standby mode is cleared WDT module standby mode control 0 WDT is set to module sta
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 SBY (low level during reset and in standby mode) PUCR1n VCC VCC PDR1n P1n PCR1n VSS Internal data bus PMR1n IRQn−4/n* PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 * n = 7 to 5 n − 4, n = 4 n Figure C.1 (a) Port 1 Block Diagram (Pins P17 to P14) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR13 VCC PMR13 PDR13 P13 VSS Internal data bus VCC PCR13 Timer G module TMIG Figure C.1 (b) Port 1 Block Diagram (Pin P13) Rev. 6.
Appendix C I/O Port Block Diagrams Timer F module SBY TMOFH (P12) TMOFL (P11) PUCR1n VCC PMR1n PDR1n P1n PCR1n VSS PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 n= 2, 1 Figure C.1 (c) Port 1 Block Diagram (Pin P12, P11) Rev. 6.
Appendix C I/O Port Block Diagrams Timer A module SBY TMOW PUCR10 VCC VCC PDR10 P10 PCR10 VSS PDR1: PCR1: PMR1: PUCR1: Internal data bus PMR10 Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (d) Port 1 Block Diagram (Pin P10) Rev. 6.
Appendix C I/O Port Block Diagrams C.2 Block Diagrams of Port 2 SBY PMR4n PDR2n P2n Internal data bus VCC PCR2n VSS PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 n = 7 to 3 Figure C.2 (a-1) Port 2 Block Diagram (Pins P27 to P23, Not Including P24 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group) Rev. 6.
Appendix C I/O Port Block Diagrams Reset signal (low level during reset) SBY PMR44 VCC PDR24 P24 Internal data bus VCC PCR24 VSS PDR2: Port data register 2 PCR2: Port control register 2 PMR4: Port mode register 4 Figure C.2 (a-2) Port 2 Block Diagram (Pin P24 in the F-ZTAT Version of the H8/38347 Group and H8/38447 Group) Rev. 6.
Appendix C I/O Port Block Diagrams SCI1 module SO1 SBY PMR25 PMR42 PMR22 P22 PDR22 VSS PCR22 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (b) Port 2 Block Diagram (Pin P22) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PMR41 PMR21 P21 PDR21 VSS Internal data bus VCC PCR21 SCI module SI PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (c) Port 2 Block Diagram (Pin P21) Rev. 6.
Appendix C I/O Port Block Diagrams SCI module EXCK SCK0 SCK1 SBY PMR40 PMR20 P20 PDR20 VSS PCR20 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PMR4: Port mode register 4 Figure C.2 (d) Port 2 Block Diagram (Pin P20) Rev. 6.
Appendix C I/O Port Block Diagrams C.3 Block Diagrams of Port 3 SBY PUCR3n VCC PMR3n P3n PDR3n VSS Internal data bus VCC PCR3n AEC module AEVH(P36) AEVL(P37) PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n=7 to 6 Figure C.3 (a) Port 3 Block Diagram (Pin P37 to P36) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR35 SCINV1 VCC SCI31 module VCC TE31 P35 PDR35 PCR35 VSS PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SCINV1: Bit 1 of serial port control register (SPCR) Figure C.3 (b) Port 3 Block Diagram (Pin P35) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR34 VCC VCC SCI31 module RE31 P34 PDR34 PCR34 VSS Internal data bus RXD31 SCINV0 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SCINV0: Bit 0 of serial port control register (SPCR) Figure C.3 (c) Port 3 Block Diagram (Pin P34) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR33 SCI31 module VCC SCKIE31 SCKOE31 VCC SCKO31 SCKI31 P33 PCR33 VSS PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 Figure C.3 (d) Port 3 Block Diagram (Pin P33) Rev. 6.
Appendix C I/O Port Block Diagrams SBY RESO PUCR32 VCC PMR32 P32 PDR32 VSS Internal data bus VCC PCR32 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e-1) Port 3 Block Diagram (Pin P32, H8/3847R Group and H8/3847S Group) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR32 VCC PMR32 P32 PDR32 VSS Internal data bus VCC PCR32 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (e-2) Port 3 Block Diagram (Pin P32, H8/38347 Group and H8/38447 Group) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PUCR31 VCC PMR31 PDR31 P31 VSS Internal data bus VCC PCR31 Timer C module UD PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C.3 (f-1) Port 3 Block Diagram (Pin P31, H8/3847R Group and H8/3847S Group)) Rev. 6.
Appendix C I/O Port Block Diagrams SBY PMR27 PUCR31 VCC PMR31 PDR31 P31 VSS Internal data bus VCC PCR31 Timer C module UD Subclock oscillator Clock input PDR3: PCR3: PMR2: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 2 Port mode register 3 Port pull-up control register 3 Figure C.3 (f-2) Port 3 Block Diagram (Pin P31, H8/38347 Group and H8/38447 Group) Rev. 6.
Appendix C I/O Port Block Diagrams PWM module SBY PWM PUCR30 VCC PMR30 P30 PDR30 VSS Internal data bus VCC PCR30 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.3 (g) Port 3 Block Diagram (Pin P30) Rev. 6.
Appendix C I/O Port Block Diagrams C.4 Block Diagrams of Port 4 Internal data bus PMR33 P43 IRQ0 PMR3: Port mode register 3 Figure C.4 (a) Port 4 Block Diagram (Pin P43) Rev. 6.
Appendix C I/O Port Block Diagrams SBY SCINV3 SCI32 module VCC TE32 TXD32 P42 PCR42 VSS Internal data bus PDR42 PDR4: Port data register 4 PCR4: Port control register 4 SCINV3: Bit 3 of serial port control register (SPCR) Figure C.4 (b) Port 4 Block Diagram (Pin P42) Rev. 6.
Appendix C I/O Port Block Diagrams SBY VCC SCI32 module RE32 RXD32 P41 PCR41 VSS SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 SCINV2: Bit 2 of serial port control register (SPCR) Figure C.4 (c) Port 4 Block Diagram (Pin P41) Rev. 6.
Appendix C I/O Port Block Diagrams SBY SCI32 module SCKIE32 SCKOE32 VCC SCKO32 SCKI32 P40 PCR40 VSS Internal data bus PDR40 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.4 (d) Port 4 Block Diagram (Pin P40) Rev. 6.
Appendix C I/O Port Block Diagrams C.5 Block Diagram of Port 5 SBY PUCR5n VCC VCC P5n PDR5n VSS PCR5n Internal data bus PMR5n WKPn PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.5 Port 5 Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.6 Block Diagram of Port 6 SBY VCC PDR6n VCC PCR6n P6n Internal data bus PUCR6n VSS PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.6 Port 6 Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.7 Block Diagram of Port 7 SBY PDR7n PCR7n P7n VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.7 Port 7 Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.8 Block Diagrams of Port 8 VCC PDR8n PCR8n P8n Internal data bus SBY VSS PDR8: Port data register 8 PCR8: Port control register 8 n= 7 to 0 Figure C.8 Port 8 Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.9 Block Diagram of Port 9 SBY PDR9n PCR9n P9n VSS PDR9: Port data register 9 PCR9: Port control register 9 n = 7 to 0 Figure C.9 Port 9 Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.10 Block Diagram of Port A SBY VCC PCRAn PAn Internal data bus PDRAn VSS PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.10 Port A Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams C.11 Block Diagram of Port B Internal data bus PBn A/D module DEC AMR3 to AMR0 VIN n = 7 to 0 Figure C.11 Port B Block Diagram Rev. 6.
Appendix C I/O Port Block Diagrams Block Diagram of Port C Internal data bus C.12 PCn A/D module DEC AMR3 to 0 VIN n = 3 to 0 Figure C.12 Port C Block Diagram Rev. 6.
Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.
Appendix E List of Product Codes Appendix E List of Product Codes Table E.
Appendix E List of Product Codes Product Type Product Code Mark Code H8/3847R H8/3845R Mask Regular Group ROM products versions HD6433845RH HD6433845R(***)H 100-pin QFP (FP-100B) HD6433845RF HD6433845R(***)F 100-pin QFP (FP-100A) HD6433845RX HD6433845R(***)X 100-pin TQFP (TFP-100B) HD6433845RW HD6433845R(***)W 100-pin TQFP (TFP100G) Package (Package Code) HCD6433845R Mask WideROM range versions specification products HD6433845RD HD6433845R(***)H 100-pin QFP (FP-100B) HD6433845RE HD64338
Appendix E List of Product Codes Product Type Product Code Mark Code H8/3847S H8/3844S Mask Regular Group ROM products versions HD6433844SH HD6433844S(***)H 100-pin QFP (FP-100B) HD6433844SX HD6433844S(***)X 100-pin TQFP (TFP-100B) HD6433844SW HD6433844S(***)W 100-pin TQFP (TFP100G) Package (Package Code) HCD6433844S Widerange specification products HD6433844SD HD6433844S(***)H 100-pin QFP (FP-100B) HD6433844SL HD6433844S(***)X 100-pin TQFP (TFP-100B) HD6433844SWI HD6433844S(***)W 100-p
Appendix E List of Product Codes Product Type H8/38347 H8/38342 Mask Regular Group ROM products versions Widerange specification products H8/38343 Mask Regular ROM products versions Widerange specification products H8/38344 Mask Regular ROM products versions Widerange specification products F-ZTAT Regular versions products Widerange specification products Product Code Mark Code Package (Package Code) HD64338342H 38342H 100-pin QFP (FP-100B) HD64338342W 38342W 100-pin TQFP (TFP100G) HD64338342X
Appendix E List of Product Codes Product Type H8/38347 H8/38345 Mask Regular Group ROM products versions Mask WideROM range versions specification products H8/38346 Mask Regular ROM products versions Widerange specification products H8/38347 Mask Regular ROM products versions Widerange specification products F-ZTAT Regular versions products Widerange specification products Product Code Mark Code Package (Package Code) HD64338345H 38345H 100-pin QFP (FP-100B) HD64338345W 38345W 100-pin TQFP (TFP
Appendix E List of Product Codes Product Type H8/38447 H8/38442 Mask Regular Group ROM products versions Widerange specification products H8/38443 Mask Regular ROM products versions Widerange specification products H8/38444 Mask Regular ROM products versions Widerange specification products F-ZTAT Regular versions products Widerange specification products Product Code Mark Code Package (Package Code) HD64338442H 38442H 100-pin QFP (FP-100B) HD64338442W 38442W 100-pin TQFP (TFP100G) HD64338442X
Appendix E List of Product Codes Product Type H8/38447 H8/38445 Mask Regular Group ROM products versions Mask WideROM range versions specification products H8/38446 Mask Regular ROM products versions Widerange specification products H8/38447 Mask Regular ROM products versions Widerange specification products F-ZTAT Regular versions products Widerange specification products Product Code Mark Code Package (Package Code) HD64338445H 38445H 100-pin QFP (FP-100B) HD64338445W 38445W 100-pin TQFP (TFP
Appendix F Package Dimensions Appendix F Package Dimensions Dimensional drawings of H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group packages FP-100A (only H8/3847R Group), FP-100B, TFP-100B and TFP-100G are shown in following figures F.1, F.2, F.3, and F.4, respectively. JEITA Package Code P-QFP100-14x20-0.65 RENESAS Code PRQP0100JE-B Previous Code FP-100A/FP-100AV MASS[Typ.] 1.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix F Package Dimensions JEITA Package Code P-QFP100-14x14-0.50 RENESAS Code PRQP0100KA-A Previous Code FP-100B/FP-100BV MASS[Typ.] 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 75 51 76 50 bp Reference Symbol c c1 HE Dimension in Millimeters Min Nom Max 14 D E 14 A2 2.70 *2 E b1 ZE Terminal cross section 1 2 5 16.0 16.3 15.7 16.0 16.3 A1 0.00 0.12 0.25 bp 0.17 0.22 0.
Appendix F Package Dimensions JEITA Package Code P-TQFP100-14x14-0.50 RENESAS Code PTQP0100KA-A Previous Code TFP-100B/TFP-100BV MASS[Typ.] 0.5g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51 76 50 bp Reference Symbol c c1 HE Dimension in Millimeters Min D Nom Max 14 E 14 A2 1.00 *2 E b1 Terminal cross section HD 15.8 16.0 16.2 HE 15.8 16.0 16.2 A1 0.00 0.10 0.20 bp 0.17 0.22 0.
Appendix F Package Dimensions JEITA Package Code P-TQFP100-12x12-0.40 RENESAS Code PTQP0100LC-A Previous Code TFP-100G/TFP-100GV MASS[Typ.] 0.4g HD *1 D 75 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 51 76 50 Reference Symbol HE b1 26 Terminal cross section ZE 100 Dimension in Millimeters Min Nom E 12 A2 1.00 HD 13.8 14.0 14.2 HE 13.8 14.0 14.2 A1 0.00 0.10 0.20 bp 0.13 0.18 0.23 1.
Appendix G Specifications of Chip Form Appendix G Specifications of Chip Form The specifications of the chip form of the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure G.1. X-direction 6.10 ± 0.05 Y-direction 6.23 ± 0.05 0.28 ± 0.22 Maximum plain X-direction 6.10 ± 0.25 Y-direction 6.23 ± 0.25 Max 0.03 (Unit: mm) Figure G.
Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64F38347 and HCD64F38447 are shown in figure G.3. X-direction 4.35 ± 0.05 Y-direction 4.83 ± 0.05 Pattern side 0.28 ± 0.22 Chip back Maximum plain X-direction 4.35 ± 0.25 Y-direction 4.83 ± 0.25 Max 0.03 (Unit: mm) Figure G.3 Chip Sectional Figure The specifications of the chip form of the H8/38347 Group (Mask ROM version) and H8/38447 Group (Mask ROM Version) are shown in figure G.4. X-direction 3.55 ± 0.
Appendix H Form of Bonding Pads Appendix H Form of Bonding Pads The form of the bonding pads for the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R is shown in figure H.1. 5 to 8 µm 90 µm Bonding area Metal Layer 90 µm 5 to 8 µm Figure H.1 Bonding Pad Form Rev. 6.
Appendix H Form of Bonding Pads The form of the bonding pads for the HCD6433847S, HCD6433846S, HCD6433845S, and HCD6433844S is shown in figure H.2. 2.5 µm 75 µm Bonding area Metal Layer 75 µm 2.5 µm Figure H.2 Bonding Pad Form Rev. 6.
Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64F38347, HCD64F38447, H8/38347 Group (Mask ROM version), and H8/38447 Group (Mask ROM version) is shown in figure H.3. Metal Layer 5 µm 65 µm Bonding area 65 µm Figure H.3 Bonding Pad Form Rev. 6.
Appendix I Specifications of Chip Tray Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD6433847R, HCD6433846R, HCD6433845R, HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure I.1. 51 Chip orientation Chip 6.23 Type code 51 6.10 Chip-tray code name Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Code name: CT054 Characteristic engraving: TCT066066-041 8.7 ± 0.1 6.6 ± 0.05 X X' 8.1 ± 0.15 6.6 ± 0.05 0.4 ± 0.1 1.8 ± 0.1 4.0 ± 0.1 8.7 ± 0.1 8.
Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD6433847S, HCD6433846S, HCD6433845S, and HCD6433844S are shown in figure I.2. 51 Chip orientation Type code Chip Base type code 3.45 51 3.55 Chip-tray code name Manufactured by DAINIPPON INK AND CHEMICALS, INCORPORATED Code name: CT065 Characteristic engraving: TCT4040-060 4.9 ± 0.1 4.0 ± 0.05 X X' 5.9 ± 0.1 4.0 ± 0.05 0.6 ± 0.1 1.8 ± 0.1 4.0 ± 0.1 4.9 ± 0.1 5.9 ± 0.
Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64F38347 and HCD64F38447 are shown in figure I.3. 51 Chip orientation Type code 4.83 Chip 51 4.35 Chip-tray code name Code name: CT037 Characteristic engraving: 2CT049049-070 5.4 ± 0.1 4.9 ± 0.05 X' X 6.6 ± 0.1 4.9 ± 0.05 0.7 ± 0.1 1.8 ± 0.1 4.0 ± 0.1 5.4 ± 0.1 6.6 ± 0.1 Cross-sectional view: X to X' (Unit: mm) Figure I.3 Specifications of Chip Tray Rev. 6.
Appendix I Specifications of Chip Tray The specifications of the chip tray for the H8/38347 Group (Mask ROM version) and H8/38447 Group (Mask ROM version) are shown in figure I.4. 51 Chip orientation Type code Chip 3.77 51 3.55 Chip-tray code name Code name: CT127 Characteristic engraving: 2CT040040-063 5.5 ± 0.1 4.0 ± 0.05 X' X 6.25 ± 0.1 4.0 ± 0.05 0.63 ± 0.05 1.8 ± 0.1 4.0 ± 0.1 5.5 ± 0.1 6.25 ± 0.1 Cross-sectional view: X to X' Figure I.4 Specifications of Chip Tray Rev. 6.
Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/3847R Group, H8/3847S Group, H8/38347 Group, H8/38447 Group Publication Date: 1st Edition, September, 1999 Rev.6.00, August 04, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/3847R Group, H8/3847S Group, H8/38347 Group, H8/38447 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0145-0600
