Datasheet

Section 2 CPU

Rev. 6.00 Aug 04, 2006 page 68 of 680

REJ09B0145-0600

Legend:

op:

rn:

IMM:

Operation field

Immediate data

15 087

RTE, SLEEP, NOP

15 087

op rn

LDC, STC (Rn)

15 087

op IMM

ANDC, ORC,

XORC, LDC (#xx:8)

Figure 2.9 System Control Instruction Codes

2.5.8 Block Data Transfer Instruction

Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.

Table 2.11 Block Data Transfer Instruction

Instruction Size Function

EEPMOV — If R4L ≠ 0 then

repeat @R5+ → @R6+

R4L –1 → R4L

until R4L = 0

else next;

Block transfer instruction. Transfers the number of data bytes

specified by R4L from locations starting at the address indicated by

R5 to locations starting at the address indicated by R6. After the

transfer, the next instruction is executed.

Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on

Use of the EEPMOV Instruction, for details.