Datasheet

Section 2 CPU
Rev. 6.00 Aug 04, 2006 page 72 of 680
REJ09B0145-0600
Three-state access to on-chip peripheral modules
T
1
state
Bus cycle
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Read data
Address
Internal
data bus
(write access)
T
2
state T
3
state
Write data
SUB
φ or φ
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)