Datasheet

Section 2 CPU
Rev. 6.00 Aug 04, 2006 page 86 of 680
REJ09B0145-0600
Read
Write
Count clock Timer counter
Timer load register
Reload
Internal bus
Figure 2.18 Timer Configuration Example
Example 2: BSET instruction executed designating port 3
P3
7
and P3
6
are designated as input pins, with a low-level signal input at P3
7
and a high-level
signal at P3
6
. The remaining pins, P3
5
to P3
0
, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P3
0
to high-level output.
[A: Prior to executing BSET]
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3 00111111
PDR3 10000000
[B: BSET instruction executed]
BSET #0 , @PDR3 The BSET instruction is executed designating port 3.