Datasheet

Section 2 CPU
Rev. 6.00 Aug 04, 2006 page 87 of 680
REJ09B0145-0600
[C: After executing BSET]
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3 00111111
PDR3 01000001
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3
7
and P3
6
are input pins, the CPU reads the pin states (low-level and high-level input).
P3
5
to P3
0
are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3
0
outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B
MOV. B
MOV. B
#H'80
R0L
R0L
,
,
,
R0L
@RAM0
@PDR3
The PDR3 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR3.
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3 00111111
PDR3 10000000
RAM0 10000000