Datasheet

Section 2 CPU
Rev. 6.00 Aug 04, 2006 page 90 of 680
REJ09B0145-0600
[B: BCLR instruction executed]
BCLR #0 , @RAM0 The BCLR instruction is executed designating the PCR3
work area (RAM0).
[C: After executing BCLR]
MOV. B
MOV. B
@RAM0,
R0L,
R0L
@PCR3
The work area (RAM0) value is written to PCR3.
P3
7
P3
6
P3
5
P3
4
P3
3
P3
2
P3
1
P3
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3 00111110
PDR3 10000000
RAM0 00111110
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.
Table 2.12 Registers with Shared Addresses
Register Name Abbr. Address
Timer counter and timer load register C TCC/TLC H'FFB5
Port data register 1
*
PDR1 H'FFD4
Port data register 2
*
PDR2 H'FFD5
Port data register 3
*
PDR3 H'FFD6
Port data register 4
*
PDR4 H'FFD7
Port data register 5
*
PDR5 H'FFD8
Port data register 6
*
PDR6 H'FFD9
Port data register 7
*
PDR7 H'FFDA
Port data register 8
*
PDR8 H'FFDB
Port data register 9
*
PDR9 H'FFDC
Port data register A
*
PDRA H'FFDD
Note: * Port data registers have the same addresses as input pins.