Datasheet

Rev. 6.00 Aug 04, 2006 page xi of xxxvi
Contents
Section 1 Overview............................................................................................................. 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 7
1.3 Pin Arrangement and Functions........................................................................................ 9
1.3.1 Pin Arrangement .................................................................................................. 9
1.3.2 Pin Functions ....................................................................................................... 32
Section 2 CPU ...................................................................................................................... 39
2.1 Overview........................................................................................................................... 39
2.1.1 Features................................................................................................................ 39
2.1.2 Address Space...................................................................................................... 40
2.1.3 Register Configuration......................................................................................... 41
2.2 Register Descriptions ........................................................................................................42
2.2.1 General Registers................................................................................................. 42
2.2.2 Control Registers ................................................................................................. 42
2.2.3 Initial Register Values.......................................................................................... 44
2.3 Data Formats..................................................................................................................... 44
2.3.1 Data Formats in General Registers ...................................................................... 45
2.3.2 Memory Data Formats ......................................................................................... 46
2.4 Addressing Modes.............................................................................................................47
2.4.1 Addressing Modes ............................................................................................... 47
2.4.2 Effective Address Calculation.............................................................................. 49
2.5 Instruction Set ................................................................................................................... 53
2.5.1 Data Transfer Instructions.................................................................................... 55
2.5.2 Arithmetic Operations.......................................................................................... 57
2.5.3 Logic Operations.................................................................................................. 58
2.5.4 Shift Operations ................................................................................................... 59
2.5.5 Bit Manipulations................................................................................................. 61
2.5.6 Branching Instructions ......................................................................................... 65
2.5.7 System Control Instructions................................................................................. 67
2.5.8 Block Data Transfer Instruction........................................................................... 68
2.6 Basic Operational Timing ................................................................................................. 70
2.6.1 Access to On-Chip Memory (RAM, ROM)......................................................... 70
2.6.2 Access to On-Chip Peripheral Modules............................................................... 71
2.7 CPU States ........................................................................................................................ 73
2.7.1 Overview.............................................................................................................. 73
2.7.2 Program Execution State...................................................................................... 75