Datasheet

Section 3 Exception Handling
Rev. 6.00 Aug 04, 2006 page 99 of 680
REJ09B0145-0600
2. Interrupt Enable Register 1 (IENR1)
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
IENS1
0
R/W
5
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
0
IEN0
0
R/W
2
IEN2
0
R/W
1
IEN1
0
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA Description
0 Disables timer A interrupt requests (initial value)
1 Enables timer A interrupt requests
Bit 6: SCI1 interrupt enable (IENS1)
Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6
IENS1 Description
0 Disables SCI1 interrupt requests (initial value)
1 Enables SCI1 interrupt requests
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP
7
to WKP
0
interrupt requests.
Bit 5
IENWP Description
0 Disables WKP
7
to WKP
0
interrupt requests (initial value)
1 Enables WKP
7
to WKP
0
interrupt requests