Datasheet

Section 3 Exception Handling
Rev. 6.00 Aug 04, 2006 page 100 of 680
REJ09B0145-0600
Bits 4 to 0: IRQ
4
to IRQ
0
interrupt enable (IEN4 to IEN0)
Bits 4 to 0 enable or disable IRQ
4
to IRQ
0
interrupt requests.
Bit n
IENn Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 4 to 0)
3. Interrupt Enable Register 2 (IENR2)
Bit
Initial value
Read/Write
7
IENDT
0
R/W
6
IENAD
0
R/W
5
—
0
R/W
4
IENTG
0
R/W
3
IENTFH
0
R/W
0
IENEC
0
R/W
2
IENTFL
0
R/W
1
IENTC
0
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT Description
0 Disables direct transfer interrupt requests (initial value)
1 Enables direct transfer interrupt requests
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD Description
0 Disables A/D converter interrupt requests (initial value)
1 Enables A/D converter interrupt requests
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.