Datasheet

Section 3 Exception Handling
Rev. 6.00 Aug 04, 2006 page 102 of 680
REJ09B0145-0600
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC Description
0 Disables asynchronous event counter interrupt requests (initial value)
1 Enables asynchronous event counter interrupt requests
For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in
section 10.3.2.
4. Interrupt Request Register 1 (IRR1)
Bit
Initial value
Read/Write
7
IRRTA
0
R/(W)
*
6
IRRS1
0
R/(W)
*
5
—
1
—
4
IRRI4
0
R/(W)
*
3
IRRI3
0
R/(W)
*
0
IRRI0
0
R/(W)
*
2
IRRI2
0
R/(W)
*
1
IRRI1
0
R/(W)
*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ
4
to IRQ
0
interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA Description
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
(initial value)
1 Setting condition:
When the timer A counter value overflows from H'FF to H'00