Datasheet

Section 3 Exception Handling
Rev. 6.00 Aug 04, 2006 page 107 of 680
REJ09B0145-0600
Bit n: WKPn edge select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn Description
0 WKPn pin falling edge detected (initial value)
1 WKPn pin rising edge detected
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts: IRQ
4
to IRQ
0
and WKP
7
to WKP
0
.
1. Interrupts WKP
7
to WKP
0
Interrupts WKP
7
to WKP
0
are requested by either rising or falling edge input to pins WKP
7
to
WKP
0
. When these pins are designated as pins WKP
7
to WKP
0
in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP
7
to WKP
0
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP
7
to WKP
0
. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
2. Interrupts IRQ
4
to IRQ
0
Interrupts IRQ4 to IRQ
0
are requested by input signals to pins IRQ
4
to IRQ
0
. These interrupts are
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG
4
to IEG
0
in IEGR.
When these pins are designated as pins IRQ
4
to IRQ
0
in port mode register 3 and 1 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN0
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ
4
to IRQ
0
interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 8 to 4 are assigned to interrupts IRQ
4
to IRQ
0
. The order of priority is from IRQ
0
(high)
to IRQ
4
(low). Table 3.2 gives details.