Datasheet

Section 3 Exception Handling
Rev. 6.00 Aug 04, 2006 page 116 of 680
REJ09B0145-0600
Table 3.5 Conditions Under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1 Conditions
IRR1 IRRI4 When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ
4
is low and IEGR
bit IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ
4
is low and IEGR
bit IEG4 = 1.
IRRI3
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ
3
is low and IEGR
bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ
3
is low and IEGR
bit IEG3 = 1.
IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ
2
is low and IEGR
bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ
2
is low and IEGR
bit IEG2 = 1.
IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ
1
is low and IEGR
bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ
1
is low and IEGR
bit IEG1 = 1.
IRRI0 When PMR3 bit IRQ0 is changed from 0 to 1 while pin IRQ
0
is low and IEGR
bit IEG0 = 0.
When PMR3 bit IRQ0 is changed from 1 to 0 while pin IRQ
0
is low and IEGR
bit IEG0 = 1.
IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP
7
is low.
IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP
6
is low.
IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP
5
is low.
IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP
4
is low.
IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP
3
is low.
IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP
2
is low.
IWPF1 When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP
1
is low.
IWPF0 When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP
0
is low.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.