Datasheet

Section 5 Power-Down Modes
Rev. 6.00 Aug 04, 2006 page 136 of 680
REJ09B0145-0600
Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose φ
OSC
/128, φ
OSC
/64, φ
OSC
/32, or φ
OSC
/16 as the operating clock in active
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0 Description
00φ
OSC
/16
01φ
OSC
/32
10φ
OSC
/64
11φ
OSC
/128 (initial value)
2. System Control Register 2 (SYSCR2)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
NESEL
1
R/W
3
DTON
0
R/W
0
SA0
0
R/W
2
MSON
0
R/W
1
SA1
0
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (φ
W
) generated by the subclock
pulse generator is sampled, in relation to the oscillator clock (φ
OSC
) generated by the system clock
pulse generator. When φ
OSC
= 2 to 16 MHz, clear NESEL to 0.
Bit 4
NESEL Description
0 Sampling rate is φ
OSC
/16
1 Sampling rate is φ
OSC
/4 (initial value)