Datasheet

Section 6 ROM
Rev. 6.00 Aug 04, 2006 page 164 of 680
REJ09B0145-0600
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Input data Output data
Verify
Address
Data
V
PP
VPP
tAS tAH
tDS tDH tDF
tOEtOEStPW
tOPW*
t
VPS
tVCS
tCES
VCC
VCC
CE
PGM
OE
V
CC
+1
VCC
Note: * t opw is defined by the value shown in fi
g
ure 6.4, Hi
g
h-Speed, Hi
g
h-Reliability Pro
g
rammin
g
Flowchart.
Figure 6.5 PROM Write/Verify Timing