Datasheet

Section 6 ROM
Rev. 6.00 Aug 04, 2006 page 175 of 680
REJ09B0145-0600
Table 6.7 Division of Blocks to Be Erased
EBR Bit Name Block (Size) Address
0 EB0 EB0 (1 Kbyte) H'0000 to H'03FF
1 EB1 EB1 (1 Kbyte) H'0400 to H'07FF
2 EB2 EB2 (1 Kbyte) H'0800 to H'0BFF
3 EB3 EB3 (1 Kbyte) H'0C00 to H'0FFF
4 EB4 EB4 (28 Kbytes) H'1000 to H'7FFF
5 EB5 EB5 (16 Kbyte) H'8000 to H'BFFF
6 EB6 EB6 (8 Kbyte) H'C000 to H'DFFF
7 EB7 EB7 (4 Kbytes) H'E000 to H'EFFF
6.6.4 Flash Memory Power Control Register (FLPWCR)
Bit 76543210
PDWND———————
Initial value00000000
Read/Write R/W ———————
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND Description
0 When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode. (initial value)
1 When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.