Datasheet

Section 6 ROM
Rev. 6.00 Aug 04, 2006 page 185 of 680
REJ09B0145-0600
Erase start
Set EBR
Enable WDT
Wait 1 µs
Wait 100 µs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
Read verify data
Increment address
Verify data = all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 µs
Wait 2 µs
EV bit ← 1
Wait 100 µs
End of erasing
SWE bit ← 0
Wait 4 µs
EV bit ← 0
n ≤100 ?
Wait 100 µs
Erase failure
SWE bit ← 0
Wait 4µs
EV bit ← 0
n ← n + 1
Yes
No
Yes
Yes
Yes
No
No
No
Figure 6.11 Erase/Erase-Verify Flowchart