Datasheet

Rev. 6.00 Aug 04, 2006 page xxiv of xxxvi
Figure 6.4 High-Speed, High-Reliability Programming Flow Chart .................................. 161
Figure 6.5 PROM Write/Verify Timing.............................................................................. 164
Figure 6.6 Recommended Screening Procedure ................................................................. 166
Figure 6.7 Block Diagram of Flash Memory ...................................................................... 168
Figure 6.8 Flash Memory Block Configuration.................................................................. 169
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode .................. 180
Figure 6.10 Program/Program-Verify Flowchart.................................................................. 182
Figure 6.11 Erase/Erase-Verify Flowchart ........................................................................... 185
Figure 6.12 Socket Adapter Pin Correspondence Diagram .................................................. 189
Figure 6.13 Timing Waveforms for Memory Read after Memory Write ............................. 191
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another
Mode.................................................................................................................. 192
Figure 6.15 CE and OE Enable State Read Timing Waveforms........................................... 192
Figure 6.16 CE and OE Clock System Read Timing Waveforms ........................................ 193
Figure 6.17 Auto-Program Mode Timing Waveforms.......................................................... 194
Figure 6.18 Auto-Erase Mode Timing Waveforms .............................................................. 196
Figure 6.19 Status Read Mode Timing Waveforms.............................................................. 197
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence............................................................................... 199
Section 7 RAM
Figure 7.1 RAM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)......... 201
Section 8 I/O Ports
Figure 8.1 Port 1 Pin Configuration.................................................................................... 205
Figure 8.2 Port 2 Pin Configuration.................................................................................... 213
Figure 8.3 Port 3 Pin Configuration.................................................................................... 219
Figure 8.4 Port 4 Pin Configuration.................................................................................... 226
Figure 8.5 Port 5 Pin Configuration.................................................................................... 230
Figure 8.6 Port 6 Pin Configuration.................................................................................... 234
Figure 8.7 Port 7 Pin Configuration.................................................................................... 238
Figure 8.8 Port 8 Pin Configuration.................................................................................... 241
Figure 8.9 Port 9 Pin Configuration.................................................................................... 244
Figure 8.10 Port A Pin Configuration................................................................................... 248
Figure 8.11 Port B Pin Configuration ................................................................................... 251
Figure 8.12 Port C Pin Configuration ................................................................................... 252
Figure 8.13 Input/Output Data Inversion Function............................................................... 253
Section 9 Timers
Figure 9.1 Block Diagram of Timer A................................................................................ 259