Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 259 of 680
REJ09B0145-0600
2. Block Diagram
Figure 9.1 shows a block diagram of timer A.
φ
PSW
Internal data bus
PSS
Legend:
TMOW
1/4
TMA
CWORS
TCA
φ
W
/32
φ
W
/16
φ
W
/8
φ
W
/4
φ/32
φ/16
φ/8
φ/4
φ /128
W
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
IRRTA
÷8* ÷64* ÷128* ÷256*
φ /4
W
TMA:
TCA:
IRRTA:
PSW:
PSS:
CWOSR:
Note: * Can be selected only when the prescaler W output (φ
W
/128) is used as the TCA input clock.
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Subclock output select register
W
φ
Figure 9.1 Block Diagram of Timer A
3. Pin Configuration
Table 9.2 shows the timer A pin configuration.
Table 9.2 Pin Configuration
Name Abbr. I/O Function
Clock output TMOW Output Output of waveform generated by timer A output circuit