Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 284 of 680
REJ09B0145-0600
Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL Description
0 Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
(initial value)
1 Setting condition:
Set when the TCFL value matches the OCRFL value
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL Description
0 TCFL overflow interrupt request is disabled (initial value)
1 TCFL overflow interrupt request is enabled
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL Description
0 TCFL clearing by compare match is disabled (initial value)
1 TCFL clearing by compare match is enabled
5. Clock Stop Register 1 (CKSTPR1)
S1CKSTP TFCKSTP TCCKSTP TACKSTPS31CKSTP S32CKSTP ADCKSTP TGCKSTP
76543210
1
1111111
R/W
R/W R/W R/W
R/W R/W R/W
R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.