Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 297 of 680
REJ09B0145-0600
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input Capture Register GF (ICRGF)
ICRGF7 ICRGF2 ICRGF1 ICRGF0ICRGF6 ICRGF5 ICRGF4 ICRGF3
76543210
0
0000000
R
RRR
RRR
R
Bit:
Initial value:
Read/Write:
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
SUB
(when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
3. Input Capture Register GR (ICRGR)
ICRGR7 ICRGR2 ICRGR1 ICRGR0ICRGR6 ICRGR5 ICRGR4 ICRGR3
76543210
0
0000000
R
RRR
RRR
R
Bit:
Initial value:
Read/Write:
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
SUB
(when the noise canceler is not used).