Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 298 of 680
REJ09B0145-0600
ICRGR is initialized to H'00 upon reset.
4. Timer Mode Register G (TMG)
OVFH CCLR0 CKS1 CKS0OVFL OVIE IIEGS CCLR1
76543210
0
0000000
R/(W)
*
R/W R/W R/W
R/(W)
*
R/W R/W
R/W
Bit:
Initial value:
Read/Write:
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH Description
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
(initial value)
1 Setting condition:
Set when TCG overflows from H'FF to H'00