Datasheet

Section 9 Timers
Rev. 6.00 Aug 04, 2006 page 300 of 680
REJ09B0145-0600
Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
Bit 2
CCLR0 Description
0 0 TCG clearing is disabled (initial value)
0 1 TCG cleared by falling edge of input capture input signal
1 0 TCG cleared by rising edge of input capture input signal
1 1 TCG cleared by both edges of input capture input signal
Bits 1 and 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
Bit 0
CKS0 Description
0 0 Internal clock: counting on φ/64 (initial value)
0 1 Internal clock: counting on φ/32
1 0 Internal clock: counting on φ/2
1 1 Internal clock: counting on φw/4
5. Clock Stop Register 1 (CKSTPR1)
S1CKSTP TFCKSTP TCCKSTP TACKSTPS31CKSTP S32CKSTP ADCKSTP TGCKSTP
76543210
1
1111111
R/W
R/W R/W R/W
R/W R/W R/W
R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.