Datasheet

Rev. 6.00 Aug 04, 2006 page xxxiii of xxxvi
Table 9.16 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching,
and Conditions for Their Occurrence ..................................................................... 309
Table 9.17 Watchdog Timer Registers..................................................................................... 313
Table 9.18 Watchdog Timer Operation States ......................................................................... 319
Table 9.19 Pin Configuration ................................................................................................... 321
Table 9.20 Asynchronous Event Counter Registers................................................................. 322
Table 9.21 Asynchronous Event Counter Operation Modes .................................................... 329
Section 10 Serial Communication Interface
Table 10.1 Overview of SCI Functions.................................................................................... 331
Table 10.2 SCI1 Pin Configuration .......................................................................................... 334
Table 10.3 Registers................................................................................................................. 334
Table 10.4 Pin Configuration ................................................................................................... 350
Table 10.5 Registers................................................................................................................. 350
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)........ 365
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)........ 366
Table 10.7 Relation between n and Clock................................................................................ 366
Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 367
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1).......... 368
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2).......... 369
Table 10.10 Relation between n and Clock................................................................................ 370
Table 10.11 SMR Settings and Corresponding Data Transfer Formats ..................................... 375
Table 10.12 SMR and SCR3 Settings and Clock Source Selection ........................................... 376
Table 10.13 Transmit/Receive Interrupts ................................................................................... 377
Table 10.14 Data Transfer Formats (Asynchronous Mode)....................................................... 380
Table 10.15 Receive Error Detection Conditions and Receive Data Processing........................ 387
Table 10.16 SCI3 Interrupt Requests ......................................................................................... 403
Table 10.17 SSR Status Flag States and Receive Data Transfer................................................ 404
Section 11 14-Bit PWM
Table 11.1 Pin Configuration ................................................................................................... 410
Table 11.2 Register Configuration ........................................................................................... 411
Table 11.3 PWM Operation Modes.......................................................................................... 416
Section 12 A/D Converter
Table 12.1 Pin Configuration ................................................................................................... 419
Table 12.2 Register Configuration ........................................................................................... 419
Table 12.3 A/D Converter Operation Modes ........................................................................... 425